公开(公告)号：EP2438619A1

公开(公告)日：2012-04-11

申请号：EP10730621.9

申请日：2010-06-03

申请人： QUALCOMM Incorporated

发明人： SONG, Seung-Chul ,  HAN, Beom-Mo ,  ABU-RAHMA, Mohamed Hassan

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  G03F7/00 ,  H01L21/3213

CPC分类号： H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/785 ,  Y10T29/41 ,  Y10T428/24479

摘要： An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.

公开(公告)号：EP2550659B1

公开(公告)日：2020-01-15

申请号：EP11713411.4

申请日：2011-03-25

申请人： Qualcomm Incorporated

发明人： JUNG, Seong-Ook ,  PARK, Hyunkook ,  SONG, Seung-Chul ,  ABU-RAHMA, Mohamed Hassan ,  GE, Lixin ,  WANG, Zhongze ,  HAN, Beom-Mo

IPC分类号： G11C11/412

公开(公告)号：EP2984756A2

公开(公告)日：2016-02-17

申请号：EP14721175.9

申请日：2014-04-04

申请人： Qualcomm Incorporated

发明人： RASOULI, Seid Hadi ,  DATTA, Animesh ,  SHAH, Jay Madhukar ,  SAINT-LAURENT, Martin ,  PARKAR, Peeyush Kumar ,  BAPAT, Sachin ,  VILANGUDIPITCHAI, Ramaprasath ,  ABU-RAHMA, Mohamed Hassan ,  PATEL, Prayag Bhanubhai

IPC分类号： H03K3/356 ,  H03K3/3562

CPC分类号： H03K3/012 ,  H03K3/356008 ,  H03K3/35625

摘要： A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

摘要翻译： 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应于逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应于控制信号来控制从站级。

公开(公告)号：EP2550659A1

公开(公告)日：2013-01-30

申请号：EP11713411.4

申请日：2011-03-25

申请人： Qualcomm Incorporated

发明人： JUNG, Seong-Ook ,  PARK, Hyunkook ,  SONG, Seung-Chul ,  ABU-RAHMA, Mohamed Hassan ,  GE, Lixin ,  WANG, Zhongze ,  HAN, Beom-Mo

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

公开(公告)号：EP2332142B1

公开(公告)日：2013-07-10

申请号：EP09792136.5

申请日：2009-09-01

申请人： QUALCOMM Incorporated

发明人： DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/16

CPC分类号： G11C11/1673

公开(公告)号：EP2353178A1

公开(公告)日：2011-08-10

申请号：EP09749294.6

申请日：2009-11-06

申请人： QUALCOMM Incorporated

发明人： SONG, Seung-Chul ,  ABU-RAHMA, Mohamed Hassan ,  HAN, Beom-Mo

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.

公开(公告)号：EP2332142A1

公开(公告)日：2011-06-15

申请号：EP09792136.5

申请日：2009-09-01

申请人： QUALCOMM Incorporated

发明人： DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/16

CPC分类号： G11C11/1673

摘要： In a particular embodiment, a memory device (100) is disclosed that includes a memory cell (226) including a resistance based memory element (228) coupled to an access transistor (230). The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier (202) configured to couple the memory cell to a supply voltage (Vamp) that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor (216) that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.