发明公开
EP2592649A1 Methods, structures and designs for self-aligning local interconnects used in integrated circuits
有权
Methode zur Herstellung selbstjustierter lokaler Interconnects in integrierten Schaltungen
- 专利标题： Methods, structures and designs for self-aligning local interconnects used in integrated circuits
- 专利标题（中）： Methode zur Herstellung selbstjustierter lokaler Interconnects in integrierten Schaltungen
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申请号： EP13154842.2申请日： 2008-10-20
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公开(公告)号： EP2592649A1公开(公告)日： 2013-05-15
- 发明人: Smayling, Michael C , Becker, Scott T
- 申请人： Tela Innovations, Inc.
- 申请人地址： 485 Alberto Way, Suite 115 Los Gatos, CA 95032 US
- 专利权人： Tela Innovations, Inc.
- 当前专利权人： Tela Innovations, Inc.
- 当前专利权人地址： 485 Alberto Way, Suite 115 Los Gatos, CA 95032 US
- 代理机构： Derry, Paul Stefan
- 优先权： US983091P 20071026; US969854 20080104
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L21/768 ; H01L21/285
摘要：
Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates (74) are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions (180). The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers (230). The method also includes designing a local interconnect layer (196) between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions (184) of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.
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