公开(公告)号：EP3358747A2

公开(公告)日：2018-08-08

申请号：EP17179613.9

申请日：2010-04-19

申请人： Tela Innovations, Inc.

发明人： BECKER, Scott T.

IPC分类号： H03K19/21 ,  G06F17/50 ,  H03K19/20

CPC分类号： H03K19/20 ,  G06F17/5068 ,  H03K19/215

摘要： An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

公开(公告)号：EP2450953A3

公开(公告)日：2017-10-11

申请号：EP11188136.3

申请日：2007-03-08

申请人： Tela Innovations, Inc.

发明人： Becker, Scott T ,  Smayling, Michael C.

IPC分类号： H01L27/10

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/28123 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/42376 ,  H01L2027/11812 ,  H01L2027/11814 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/11862 ,  H01L2027/11864 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

摘要翻译： 一种半导体器件包括衬底和限定在衬底内的多个扩散区。 扩散区域通过衬底的非有源区域彼此分离。 半导体器件包括多个线性栅电极迹线，其被限定为在单个公共方向上在衬底上方延伸。 每个线性栅极电极轨道由一个或多个线性栅极电极段限定。 限定在衬底的扩散区域和非活性区域两者上延伸的每个线性栅极电极迹线以使线性栅极电极迹线内的相邻线性栅极电极段的端部之间的间隔距离最小化，同时确保在 相邻的线性栅极电极段。

公开(公告)号：EP3188217A3

公开(公告)日：2017-08-02

申请号：EP17151880.6

申请日：2008-10-20

申请人： Tela Innovations, Inc.

发明人： Smayling, Michael C ,  Becker, Scott T

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/092 ,  G03F1/14 ,  G06F17/5077 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

公开(公告)号：EP2592649A1

公开(公告)日：2013-05-15

申请号：EP13154842.2

申请日：2008-10-20

申请人： Tela Innovations, Inc.

发明人： Smayling, Michael C ,  Becker, Scott T

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L27/092 ,  G03F1/14 ,  G06F17/5077 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates (74) are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions (180). The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers (230). The method also includes designing a local interconnect layer (196) between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions (184) of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

摘要翻译： 提供了自对准局部互连的方法，结构和设计。 该方法包括将扩散区域设计在衬底中。 多个栅极（74）中的一些被设计为有源栅极，并且多个栅极中的一些被设计为形成在隔离区域（180）上。 该方法包括沿相同方向以规则且重复的对准来设计多个栅极，并且多个栅极中的每一个被设计成具有电介质间隔物（230）。 该方法还包括在多个门之间或邻近设计局部互连层（196）。 局部互连层是导电的并且设置在衬底上，以允许与有源栅极的一些扩散区域（184）的电接触和互连。 局部互连层通过多个栅极的介电间隔物自对准。

公开(公告)号：EP2425531B1

公开(公告)日：2016-01-13

申请号：EP10716951.8

申请日：2010-04-19

申请人： Tela Innovations, Inc.

发明人： BECKER, Scott, T.

IPC分类号： G06F17/50 ,  H03K19/20 ,  H03K19/21

CPC分类号： H03K19/20 ,  G06F17/5068 ,  H03K19/215

公开(公告)号：EP2592648A1

公开(公告)日：2013-05-15

申请号：EP13154840.6

申请日：2008-10-20

申请人： Tela Innovations, Inc.

发明人： Smayling, Michael C ,  Becker, Scott T

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L27/092 ,  G03F1/14 ,  G06F17/5077 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates (74, 74a, 74b) are designed to be active gates (74) and some of the plurality of gates (74a, 74b) are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer (196, 196') between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions (64, 68) of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

摘要翻译： 提供一些方法，结构和设计的自对准局部互连。 该方法包括设计的扩散区是在一个基片。 一些门的多个（74，74A，74B）被设计为有源栅极（74）和一些门的多个（74A，74B）被设计为形成在隔离区。 该方法包括设计门中的多个沿同一方向上具有规则和重复的排列，并且每个栅的多个被设计成具有介电间隔件。 因此，该方法包括之间或邻近于栅极的多元性设计局部互连层（196，196“）。 局部互连层是导电的，并且设置在所述基片，以允许电接触和互连或连接到一些所述有源栅极的扩散区域（64，68）的。 局部互连层是自对准通过门的多个所述电介质间隔物。

公开(公告)号：EP2450953A2

公开(公告)日：2012-05-09

申请号：EP11188136.3

申请日：2007-03-08

申请人： Tela Innovations, Inc.

发明人： Becker, Scott T ,  Smayling, Michael C.

IPC分类号： H01L27/02 ,  G06F17/50

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/28123 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/42376 ,  H01L2027/11812 ,  H01L2027/11814 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/11862 ,  H01L2027/11864 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

摘要翻译： 半导体器件包括衬底和限定在衬底内的多个扩散区域。 扩散区域通过衬底的非有源区域彼此分离。 半导体器件包括多个线性栅极电极轨道，其被限定为在单个共同方向上在衬底上延伸。 每个线性栅极电极轨道由一个或多个线性栅电极段限定。 限定在衬底的扩散区域和非有源区域上延伸的每个线性栅极电极轨迹，以使线性栅极电极轨道内的相邻线性栅电极段的端部之间的间隔距离最小化，同时确保 相邻的线性栅电极段。

公开(公告)号：EP2206146A2

公开(公告)日：2010-07-14

申请号：EP08842026.0

申请日：2008-10-20

申请人： Tela Innovations, Inc.

发明人： SMAYLING, Michael, C. ,  BECKER, Scott, T.

IPC分类号： H01L21/8238

CPC分类号： H01L27/092 ,  G03F1/14 ,  G06F17/5077 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates (74) are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions (180). The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers (230). The method also includes designing a local interconnect layer (196) between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions (184) of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

公开(公告)号：EP1999793A4

公开(公告)日：2009-11-11

申请号：EP07752875

申请日：2007-03-08

申请人： TELA INNOVATIONS INC

发明人： BECKER SCOTT T ,  SMAYLING MICHAEL C

IPC分类号： H01L27/10

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/28123 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/42376 ,  H01L2027/11812 ,  H01L2027/11814 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/11862 ,  H01L2027/11864 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

公开(公告)号：EP3358747A3

公开(公告)日：2018-11-14

申请号：EP17179613.9

申请日：2010-04-19

申请人： Tela Innovations, Inc.

发明人： BECKER, Scott T.

IPC分类号： H03K19/21 ,  G06F17/50 ,  H03K19/20

CPC分类号： H03K19/20 ,  G06F17/5068 ,  H03K19/215

摘要： An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.