发明公开
EP3084812A4 NMOS AND PMOS STRAINED DEVICES WITHOUT RELAXED SUBSTRATES
审中-公开
NMOS-UND PMOS-VORGESPANNTE VORRICHTUNGEN OHNE柔性衬底
- 专利标题: NMOS AND PMOS STRAINED DEVICES WITHOUT RELAXED SUBSTRATES
- 专利标题(中): NMOS-UND PMOS-VORGESPANNTE VORRICHTUNGEN OHNE柔性衬底
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申请号: EP13899638申请日: 2013-12-16
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公开(公告)号: EP3084812A4公开(公告)日: 2017-08-09
- 发明人: CEA STEPHEN M , KOTLYAR ROZA , KENNEL HAROLD W , MURTHY ANAND S , GLASS GLENN A , KUHN KELIN J , GHANI TAHIR
- 申请人: INTEL CORP
- 专利权人: INTEL CORP
- 当前专利权人: INTEL CORP
- 优先权: US2013075452 2013-12-16
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238 ; H01L21/84 ; H01L27/092 ; H01L27/12 ; H01L29/04 ; H01L29/10 ; H01L29/165 ; H01L29/66 ; H01L29/778
摘要:
Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
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