公开(公告)号：EP3084812A4

公开(公告)日：2017-08-09

申请号：EP13899638

申请日：2013-12-16

申请人： INTEL CORP

发明人： CEA STEPHEN M ,  KOTLYAR ROZA ,  KENNEL HAROLD W ,  MURTHY ANAND S ,  GLASS GLENN A ,  KUHN KELIN J ,  GHANI TAHIR

IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66818 ,  H01L29/7781 ,  H01L29/7782

摘要： Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

摘要翻译： 涉及没有松弛衬底的应变NMOS和PMOS器件的技术和方法，包含这种半导体器件的系统及其方法。

公开(公告)号：EP2920815A4

公开(公告)日：2016-10-12

申请号：EP13854345

申请日：2013-06-12

申请人： INTEL CORP

发明人： KOTLYAR ROZA ,  CEA STEPHEN M ,  DEWEY GILBERT ,  CHU-KUNG BENJAMIN ,  AVCI UYGAR E ,  RIOS RAFAEL ,  CHAUDHRY ANURAG ,  LINTON JR THOMAS D ,  YOUNG IAN A ,  KUHN KELIN J

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/739

CPC分类号： H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

公开(公告)号：EP2878013A4

公开(公告)日：2015-12-30

申请号：EP13822277

申请日：2013-06-12

申请人： INTEL CORP

发明人： CEA STEPHEN M ,  MURTHY ANAND S ,  GLASS GLENN A ,  AUBERTINE DANIEL B ,  GHANI TAHIR ,  KAVALIEROS JACK T ,  KOTLYAR ROZA

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/165

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

公开(公告)号：EP2517254A4

公开(公告)日：2013-10-02

申请号：EP10843439

申请日：2010-12-02

申请人： INTEL CORP

发明人： CEA STEPHEN M ,  MEHANDRU RISHABH ,  SHIFREN LUCIAN ,  KUHN KELIN

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7858

公开(公告)号：EP3123518A4

公开(公告)日：2017-11-22

申请号：EP14887192

申请日：2014-03-27

申请人： INTEL CORP

发明人： CEA STEPHEN M ,  KOTLYAR ROZA ,  KENNEL HAROLD W ,  GLASS GLENN A ,  MURTHY ANAND S ,  RACHMADY WILLY ,  GHANI TAHIR

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：EP2647038A4

公开(公告)日：2015-01-07

申请号：EP11844167

申请日：2011-11-23

申请人： INTEL CORP

发明人： KUHN KELIN J ,  KIM SEIYON ,  RIOS RAFAEL ,  CEA STEPHEN M ,  GILES MARTIN D ,  CAPPELLANI ANNALISA ,  RAKSHIT TITASH ,  CHANG PETER ,  RACHMADY WILLY

IPC分类号： H01L21/336 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

公开(公告)号：EP3084834A4

公开(公告)日：2017-08-02

申请号：EP13899827

申请日：2013-12-16

申请人： INTEL CORP

发明人： CEA STEPHEN M ,  KOTLYAR ROZA ,  KENNEL HAROLD W ,  KUHN KELIN J ,  GHANI TAHIR

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.

摘要翻译： 涉及用于半导体器件的双应变覆层的技术和方法，以及包含这种半导体器件的系统。

公开(公告)号：EP3050091A4

公开(公告)日：2017-05-10

申请号：EP13894881

申请日：2013-09-27

申请人： INTEL CORP

发明人： PILLARISETTY RAVI ,  DASGUPTA SANSAPTAK ,  GOEL NITI ,  LE VAN H ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT ,  MUKHERJEE NILOY ,  METZ MATTHEW V ,  RACHMADY WILLY ,  KAVALIEROS JACK T ,  CHU-KUNG BENJAMIN ,  KENNEL HAROLD W ,  CEA STEPHEN M ,  CHAU ROBERT S

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

摘要翻译： 描述了具有最大顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底上方的半导体鳍片。 半导体鳍状物具有沿着半导体鳍状物的长度与一对突出外部分隔开的中央突出或凹陷部分。 覆层层区域设置在半导体鳍片的中央突出或凹陷部分上。 栅极叠层设置在包层区域上。 源极/漏极区域设置在半导体鳍状物的一对突出的外部区段中。

公开(公告)号：EP2619797A4

公开(公告)日：2016-04-06

申请号：EP11827279

申请日：2011-09-19

申请人： INTEL CORP

发明人： CEA STEPHEN M ,  KOTLYAR ROZA ,  KAVALIEROS JACK T ,  GILES MARTIN D ,  GHANI TAHIR ,  KUHN KELIN J ,  KUHN MARKUS ,  ZELICK NANCY M

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10

CPC分类号： H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

摘要翻译： 一种方法和雅丁的方法制成的设备。 该方法包括提供一基板，其包括第一材料，以及提供一鳍包括第二材料，所述翅片被在基板上设置，并且具有器件活性部分，所述第一材料和所述第二材料呈现respectivement晶体结构及其之间的晶格失配 ， 提供所述鳍包括提供双轴应变电影包含基板上的第二材料; 和去除所述双轴应变电影的部分从那里形成基本上单轴应变片。