发明公开
- 专利标题： METHOD OF MANAGING MEMORIES, CORRESPONDING DEVICE AND APPARATUS
- 专利标题（中）： 的管理方法辐条，相关设备和设置
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申请号： EP16162366.5申请日： 2016-03-24
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公开(公告)号： EP3139275A1公开(公告)日： 2017-03-08
- 发明人: MANGANO, Daniele , CARRANO, Michele Alessandro , DISTEFANO, Gaetano , FRIED, Antonin
- 申请人： STMicroelectronics Design and Application s.r.o. , STMicroelectronics S.r.l.
- 申请人地址： Pobrezni 620/3 186 00 Praha 8 CZ
- 专利权人： STMicroelectronics Design and Application s.r.o.,STMicroelectronics S.r.l.
- 当前专利权人： STMicroelectronics Design and Application s.r.o.,STMicroelectronics S.r.l.
- 当前专利权人地址： Pobrezni 620/3 186 00 Praha 8 CZ
- 代理机构： Bosotti, Luciano
- 优先权： ITUB20153367 20150903
- 主分类号： G06F11/10
- IPC分类号： G06F11/10
摘要：
In an embodiment, a method of managing memories (10) includes:
- providing a first (11) memory module and a second memory module (12) each including a first (R1, R2) and a second (R4, R3) partition,
- writing first data (DATA1) in the first partition (R1) of the first memory module (11) and second data (DATA2) in the first partition (R2) of the second memory module (12), and
- selectively operating the first (11) and second (12) memory modules in a first operating mode or a second operating mode, where:
- in the first operating mode, parity bits (PAR1) for the first data (DATA1) are written in the second partition (R3) of the second memory module (12) and parity bits (PAR2) for the second data (DATA2) are written in the second partition (R4) of the first memory module (11),
- in the second operating mode, further data (ED1, ED2) are written in the place of parity bits (PAR1, PAR2) in the second partition (R4, R3) of one or both the first memory module (11) and the second memory module (12).
- providing a first (11) memory module and a second memory module (12) each including a first (R1, R2) and a second (R4, R3) partition,
- writing first data (DATA1) in the first partition (R1) of the first memory module (11) and second data (DATA2) in the first partition (R2) of the second memory module (12), and
- selectively operating the first (11) and second (12) memory modules in a first operating mode or a second operating mode, where:
- in the first operating mode, parity bits (PAR1) for the first data (DATA1) are written in the second partition (R3) of the second memory module (12) and parity bits (PAR2) for the second data (DATA2) are written in the second partition (R4) of the first memory module (11),
- in the second operating mode, further data (ED1, ED2) are written in the place of parity bits (PAR1, PAR2) in the second partition (R4, R3) of one or both the first memory module (11) and the second memory module (12).
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