发明公开
EP3174061A1 MEMORY CIRCUIT PROVIDED WITH BISTABLE CIRCUIT AND NON-VOLATILE ELEMENT
有权
存储电路提供双稳态电路和非易失性元件
- 专利标题： MEMORY CIRCUIT PROVIDED WITH BISTABLE CIRCUIT AND NON-VOLATILE ELEMENT
- 专利标题（中）： 存储电路提供双稳态电路和非易失性元件
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申请号： EP17151073.8申请日： 2013-02-19
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公开(公告)号： EP3174061A1公开(公告)日： 2017-05-31
- 发明人: SHUTO, Yusuke , YAMAMOTO, Shuichiro , SUGAHARA, Satoshi
- 申请人： Japan Science and Technology Agency
- 申请人地址： 1-8, Honcho 4-chome Kawaguchi-shi Saitama 332-0012 JP
- 专利权人： Japan Science and Technology Agency
- 当前专利权人： Japan Science and Technology Agency
- 当前专利权人地址： 1-8, Honcho 4-chome Kawaguchi-shi Saitama 332-0012 JP
- 代理机构： Cabinet Plasseraud
- 优先权： JP2012114989 20120518
- 主分类号： G11C11/15
- IPC分类号： G11C11/15 ; G11C11/412 ; G11C14/00
摘要：
A memory circuit comprising:
a bistable circuit (30) configured to write data;
a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit (30) by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL);
an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CNTL); and
a control unit (85) configured to make a voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a supply voltage to be applied to the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.
a bistable circuit (30) configured to write data;
a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit (30) by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL);
an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CNTL); and
a control unit (85) configured to make a voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a supply voltage to be applied to the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.
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