公开(公告)号：EP3979499A1

公开(公告)日：2022-04-06

申请号：EP20812785.2

申请日：2020-03-18

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  KITAGATA, Daiki ,  YAMAMOTO, Shuichiro

IPC分类号： H03K3/356 ,  G11C14/00 ,  G11C11/412 ,  G11C11/417

摘要： Provided is an electronic circuit including a cell array including memory cells each including a bistable circuit that includes a first inverter circuit and a second inverter circuit, each of the first inverter circuit and the second inverter circuit having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in transfer characteristics, wherein each of the first inverter circuit and the second inverter circuit are configured to be switchable between the first mode and the second mode, an output node and an input node of the first inverter circuit being coupled to an input node and an output node of the second inverter circuit, respectively, and a control circuit configured to, after powering off one or more first memory cells that are not required to retain data among the memory cells, put the bistable circuits in remaining one or more second memory cells of the memory cells into the second mode, and supply a second power supply voltage, at which the bistable circuit in the second mode can retain data, to the bistable circuits in the one or more second memory cells while maintaining the second mode, the second power supply voltage being lower than a first power supply voltage that is supplied to the bistable circuit when data is read and/or written.

公开(公告)号：EP4297109A1

公开(公告)日：2023-12-27

申请号：EP22756150.3

申请日：2022-02-15

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  KUMAGAI, Hayato

IPC分类号： H01L35/32 ,  H02N11/00

摘要： A thermoelectric conversion device includes first thermoelectric layers and second thermoelectric layers that are alternately provided in a first direction parallel to surfaces of the first thermoelectric layers and the second thermoelectric layers, the first thermoelectric layers having conductivity types opposite to those of the second thermoelectric layers, first connection layers and second connection layers that are electrically and thermally connected to the first thermoelectric layers and the second thermoelectric layers between the first thermoelectric layers and the second thermoelectric layers, the first connection layers and the second connection layers being alternately provided in the first direction, first thermally conductive layers that are thermally connected to the first connection layers, the first thermally conductive layers extending in a second direction intersecting the surfaces, a first insulating layer through which the first thermally conductive layers penetrate, the first insulating layer having a thermal conductivity smaller than thermal conductivities of the first thermally conductive layers, a second insulating layer through which the first thermally conductive layers penetrate, the second insulating layer having a thermal conductivity smaller than the thermal conductivity of the first insulating layer, the second insulating layer being provided between the first insulating layer and the first thermoelectric layers and the second thermoelectric layers, the second insulating layer having a thickness equal to or greater than 1/4 of a larger distance of a distance between an end of the first thermally conductive layer at a side of the first thermoelectric layer and a center of the second connection layer in the first direction and a distance between an end of the first thermally conductive layer at a side of the second thermoelectric layer and the center of the second connection layer in the first direction.

公开(公告)号：EP4105932A1

公开(公告)日：2022-12-21

申请号：EP21753980.8

申请日：2021-01-29

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  SHIOTSU, Yusaku

IPC分类号： G11C11/412 ,  G06F12/00 ,  G06N3/063 ,  G11C5/14 ,  G11C7/10 ,  G11C7/18 ,  G11C14/00 ,  H03K3/356 ,  H03K3/3565

摘要： A bistable circuit includes a first inverter circuit and a second inverter circuit each including a first FET having a channel of a first conductivity type, wherein a source of the first FET is coupled to a power supply line, a drain of the first FET is coupled to an intermediate node, and a gate of the first FET is coupled to an input node, a second FET having a channel of the first conductivity type, wherein a source of the second FET is coupled to the intermediate node, and a drain of the second FET is coupled to an output node, a third FET, wherein one of a source and a drain of the third FET is coupled to the intermediate node, and the other of the source and the drain of the third FET is coupled to a bias node, a fourth FET having a channel of a second conductivity type opposite to the first conductivity type, wherein one of a source and a drain of the fourth FET is coupled to the output node, and the other of the source and the drain of the fourth FET is coupled to a control line, a first memory node to which an input node of the first inverter circuit and an output node of the second inverter circuit are coupled, and a second memory node to which an output node of the first inverter circuit and an input node of the second inverter circuit are coupled, wherein gates of the fourth FETs of the first inverter circuit and the second inverter circuit are coupled to a word line, wherein a gate of the third FET of the first inverter circuit is coupled to one of the following nodes: the input node and the output node of the first inverter circuit and the input node and the output node of the second inverter circuit, and wherein a gate of the third FET of the second inverter circuit is coupled to one of the following nodes: the input node and the output node of the second inverter circuit and the input node and the output node of the first inverter circuit.

公开(公告)号：EP3174061A1

公开(公告)日：2017-05-31

申请号：EP17151073.8

申请日：2013-02-19

申请人： Japan Science and Technology Agency

发明人： SHUTO, Yusuke ,  YAMAMOTO, Shuichiro ,  SUGAHARA, Satoshi

IPC分类号： G11C11/15 ,  G11C11/412 ,  G11C14/00

摘要： A memory circuit comprising:
a bistable circuit (30) configured to write data;
a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit (30) by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL);
an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CNTL); and
a control unit (85) configured to make a voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a supply voltage to be applied to the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.

摘要翻译： 一种存储器电路，包括：双稳态电路（30），被配置为写入数据; 非易失性元件（MTJ1，MTJ2），其被配置为以非易失性方式存储写入双稳态电路（30）中的数据，并且通过利用在一个电流之间流动的电流来改变电阻值来将以非易失性方式存储的数据恢复到双稳态电路 一端连接到双稳态电路（30）的节点（Q，QB），另一端连接到控制线（CTRL）的非易失性元件（MTJ1，MTJ2）; 在节点（Q，QB）和控制线（CNTL）之间具有与非易失性元件（MTJ1，MTJ2）串联连接的源极和漏极的FET（m7，m8） 以及控制单元（85），其被配置为在一段时间期间使得施加到FET（m7，m8）的栅极的电压（SR）以非易失性方式将存储在非易失性元件（MTJ1，MTJ2）中的数据恢复成 所述双稳态电路（30）在挥发性地向所述双稳态电路（30）写入数据和从所述双稳态电路（30）读取数据期间施加到所述双稳态电路（30）的电源电压低。

公开(公告)号：EP3118906A1

公开(公告)日：2017-01-18

申请号：EP15761845.5

申请日：2015-03-06

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  SHUTO, Yusuke ,  KUROSAWA, Minoru ,  FUNAKUBO, Hiroshi ,  YAMAMOTO, Shuichiro

IPC分类号： H01L45/00 ,  G11C11/15 ,  G11C13/00 ,  H03K3/356

CPC分类号： H01L49/00 ,  G11C11/16 ,  G11C14/0081 ,  G11C14/009 ,  H01L27/226 ,  H01L27/2436 ,  H03K3/356

摘要： Provided is a transistor including: a piezoresistor 10 through which carriers conduct; a source 14 that injects the carriers into the piezoresistor; a drain 16 that receives the carriers from the piezoresistor; a piezoelectric material 12 that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate 18 that applies a voltage to the piezoelectric material applies so that the piezoelectric material applies a pressure to the piezoresistor.

摘要翻译： 提供一种晶体管，包括：载流子导体通过的压电电阻器10; 将载流子注入到压电电阻器中的源极14; 漏极16，其从压电电阻器接收载流子; 定位成围绕压电电阻并对压敏电阻施加压力的压电材料12; 并且施加向压电材料施加电压的栅极18，使得压电材料向压电电阻器施加压力。

公开(公告)号：EP3109863A1

公开(公告)日：2016-12-28

申请号：EP16180034.7

申请日：2013-02-19

申请人： Japan Science and Technology Agency

发明人： YAMAMOTO, Shuichiro ,  SHUTO, Yusuke ,  SUGAHARA, Satoshi

IPC分类号： G11C11/16 ,  G11C14/00 ,  G11C13/00

CPC分类号： G11C14/0081 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0069 ,  G11C14/0054 ,  G11C2013/0076 ,  G11C2207/2263

摘要： A memory circuit includes: a ferromagnetic tunnel junction device, a readout circuit configured to read out data written into the ferromagnetic tunnel junction device in a nonvolatile manner, and a control unit configured not to write data to be written in a nonvolatile manner into the ferromagnetic tunnel junction device when an output of the readout circuit is the same as the data to be written into the ferromagnetic tunnel junction device in a nonvolatile manner, and configured to write the data to be written in a nonvolatile manner into the ferromagnetic tunnel junction device when the output of the readout circuit is not the same as the data to be written in a nonvolatile manner.

摘要翻译： 一种存储器电路包括：铁磁隧道结器件;读出电路，被配置为以非易失性方式读出写入到铁磁隧道结器件中的数据;以及控制单元，被配置为不写入要以非易失性方式写入到铁磁体中的数据 当所述读出电路的输出与要被非易失性地写入所述铁磁隧道结器件的数据相同时，所述隧道结器件被配置为当要写入的数据以非易失性的方式写入到所述铁磁隧道结器件中时 读出电路的输出与要以非易失性方式写入的数据不同。

公开(公告)号：EP3107105A1

公开(公告)日：2016-12-21

申请号：EP16181451.2

申请日：2013-02-19

申请人： Japan Science and Technology Agency

发明人： YAMAMOTO, Shuichiro ,  SHUTO, Yusuke ,  SUGAHARA, Satoshi

IPC分类号： G11C14/00 ,  G11C11/16 ,  G11C13/00

CPC分类号： G11C14/0081 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0069 ,  G11C14/0054 ,  G11C2013/0076 ,  G11C2207/2263

摘要： A memory circuit includes a plurality of memory cells each including a bistable circuit configured to write data, and a nonvolatile element configured to store the data written in the bistable circuit in a nonvolatile manner and restore the data stored in a nonvolatile manner into the bistable circuit; and a control unit configured to determine whether the data in the bistable circuit is the same as data in the nonvolatile element in each memory cell of the plurality of memory cells.

摘要翻译： 存储器电路包括多个存储单元，每个存储单元包括配置为写入数据的双稳态电路，以及非易失性元件，其被配置为以非易失性方式存储写入双稳态电路中的数据，并将以非易失性方式存储的数据恢复到双稳态电路 ; 以及控制单元，被配置为确定双稳态电路中的数据是否与多个存储单元的每个存储单元中的非易失性元件中的数据相同。

公开(公告)号：EP1610386A1

公开(公告)日：2005-12-28

申请号：EP04724405.8

申请日：2004-03-30

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  TANAKA, Masaaki

IPC分类号： H01L27/105 ,  H01L43/08

CPC分类号： H01F10/3254 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01F1/405 ,  H01F10/193 ,  H01L27/228 ,  H01L29/66984

摘要： A MISFET the channel region of which is a ferromagnetic semiconductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration.

摘要翻译： 其沟道区域是铁磁半导体的MISFET具有可以通过栅极电压来控制漏极电流的特征，并且具有可以通过铁磁通道区域和铁磁源中的相对磁化方向来控制转移电导的特征 （或铁磁性漏极，或铁磁源和铁磁性漏极）。 结果，可以以相对磁化方向的形式存储二进制信息，并且电检测相对磁化方向。 如果磁性由铁磁半导体的沟道区域的电场效应控制，那么可以大大减少重写信息所需的电流。 因此，MISFET可以构成适合于高密度集成的高性能非易失性存储单元。

公开(公告)号：EP1555694A1

公开(公告)日：2005-07-20

申请号：EP03771333.6

申请日：2003-07-25

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  TANAKA, Masaaki

IPC分类号： H01L29/82 ,  H01L43/08 ,  H01L27/105

CPC分类号： H01L29/66984 ,  G11C11/15 ,  G11C11/16 ,  H01L29/73 ,  H01L29/778 ,  H01L29/78 ,  H01L43/08

摘要： A spin transistor comprises a spin injector for injecting, from a first nonmagnetic electrode carriers with a spin parallel to a spin band forming the band edge of a first ferromagnetic barrier layer, to a second nonmagnetic electrode layer, as hot carriers. It also comprises a spin analyzer whereby, due to spin-splitting at the band edge of a second ferromagnetic barrier layer, the spin-polarized hot carriers are transported to a third nonmagnetic electrode when the direction of the spin of the carriers injected into the second nonmagnetic electrode is parallel to that of the spin of the spin band at the band edge of the second ferromagnetic barrier layer, whereas the hot carriers are not transported to the third nonmagnetic electrode in the case of antiparallel spin. A memory element is also provided that comprises such a spin transistor.

摘要翻译： 自旋晶体管包括自旋注入器，用于从与形成第一铁磁阻挡层的带边缘的平行于自旋带的自旋的第一非磁性电极载体作为热载流子注入到第二非磁性电极层。 它还包括自旋分析器，由此由于在第二铁磁阻挡层的带边缘处的自旋分裂，当注入第二铁磁阻挡层的载流子的自旋方向被转移到第三非磁性电极时，自旋极化热载流子被传送到第三非磁性电极 非磁性电极平行于第二铁磁阻挡层的带边缘处的自旋带的自旋，而在反向并联旋转的情况下，热载流子不被传送到第三非磁性电极。 还提供了包括这种自旋晶体管的存储元件。

公开(公告)号：EP3828889A1

公开(公告)日：2021-06-02

申请号：EP20214620.5

申请日：2015-08-06

申请人： Japan Science and Technology Agency

发明人： SUGAHARA, Satoshi ,  SHUTO, Yusuke ,  YAMAMOTO, Shuichiro

IPC分类号： G11C11/15 ,  G11C11/412 ,  G11C14/00 ,  G11C11/16

摘要： Provided is a memory circuit including: a plurality of cells arranged in a plurality of rows and a plurality of columns so that the plurality of rows are grouped to form a plurality of banks each including one or more rows, each of the plurality of cells including: a bistable circuit configured to store data; and a non-volatile element configured to store data stored in the bistable circuit in a non-volatile manner and to restore data stored in a non-volatile manner to the bistable circuit; and a controller configured to: perform a store operation on each of the plurality of rows in turn; set a voltage supplied, as a power-supply voltage, to cells in a first bank of the plurality of banks to a first voltage, the first bank including a row on which the store operation is performed; and set a voltage supplied, as a power-supply voltage, to cells in a bank of the plurality of banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.