A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.