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    PSEUDO MULTI-PORT MEMORY WITH MEMORY CELLS EACH HAVING TWO-PORT MEMORY CELL ARCHITECTURE AND MULTIPLE ENABLE PULSES ON SAME WORDLINE AND ASSOCIATED MEMORY ACCESS METHOD
    1.
    发明公开
    PSEUDO MULTI-PORT MEMORY WITH MEMORY CELLS EACH HAVING TWO-PORT MEMORY CELL ARCHITECTURE AND MULTIPLE ENABLE PULSES ON SAME WORDLINE AND ASSOCIATED MEMORY ACCESS METHOD 审中-公开

    公开(公告)号：EP4343764A1

    公开(公告)日：2024-03-27

    申请号：EP23193385.4

    申请日：2023-08-25

    Applicant: MediaTek Inc.

    Inventor： LIAO, Weinan ,  HONG, Chi-Hao

    IPC: G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412

    Abstract: A pseudo multi-port memory includes a memory array, a row decoder circuit, a timing controller circuit, a sense amplifier circuit, and a write driver circuit. The timing controller circuit outputs a timing control signal to the row decoder circuit, wherein during one memory clock cycle, the row decoder circuit is controlled by the timing control signal to make a read wordline (RWL) signal have an enable pulse and a write wordline (WWL) signal have multiple enable pulses. During one memory clock cycle, the sense amplifier circuit performs read operations upon a selected memory cell when the selected RWL is enabled by the enable pulse and the selected WWL is enabled by at least one first enable pulse, and the write driver circuit performs a write operation upon the selected memory cell when the selected WWL is enabled by one second enable pulse.

    TWO-PORT TERNARY CONTENT ADDRESSABLE MEMORY
    4.
    发明公开
    TWO-PORT TERNARY CONTENT ADDRESSABLE MEMORY 审中-公开

    公开(公告)号：EP4216219A1

    公开(公告)日：2023-07-26

    申请号：EP23159961.4

    申请日：2020-04-07

    Applicant: United Microelectronics Corp.

    Inventor： HUANG, Chun-Hsien ,  LUNG, Ching-Cheng ,  KUO, Yu-Tse ,  WANG, Shu-Ru ,  TSENG, Chun-Yen

    IPC: G11C8/16 ,  G11C15/04

    Abstract: A two-port ternary content addressable memory (TCAM) cell, comprising: a first storage unit, configured to store a first bit of a content data, wherein the first storage unit comprises a first storage node and a first inverted storage node; a second storage unit, configured to store a second bit of the content data, wherein the second storage unit comprises a second storage node and a second inverted storage node; a set of first search terminals, configured to input a first search data into the two-port TCAM; a set of second search terminals, configured to input a second search data into the two-port TCAM; a first comparison circuit, respectively coupled to the first storage node of the first storage unit, the second storage node of the second storage unit and the set of first search terminals, configured to determine whether the first search data matches the content data and accordingly generate a first determination result; a second comparison circuit, respectively coupled to the first inverted storage node of the first storage unit, the second inverted storage node of the second storage unit and the set of second search terminals, configured to determine whether the second search data matches the content data and accordingly generate a second determination result; a first match terminal, coupled to the first comparison circuit, configured to output the first determination result; and a second match terminal, coupled to the second comparison circuit, configured to output the second determination result; wherein the first search data and the second search data are concurrently inputted into the two-port TCAM, and the first determination result and the second determination result are concurrently outputted.

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