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    PSEUDO DUAL PORT MEMORY
    1.
    发明公开
    PSEUDO DUAL PORT MEMORY 有权
    PSEUDO双端口存储器

    公开(公告)号：EP3195318A1

    公开(公告)日：2017-07-26

    申请号：EP15748352.0

    申请日：2015-07-20

    申请人： Qualcomm Incorporated

    发明人： YOON, Sei Seung ,  KWOK, Tony Chung Yiu ,  JUNG, Changho ,  DESAI, Nishith Nitin

    IPC分类号： G11C7/10 ,  G11C8/16

    CPC分类号： G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

    摘要： A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

    摘要翻译： 存储器和操作提供的存储器的方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路被配置为响应访问周期的时钟的边沿来产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括一个锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。

    PSEUDO DUAL PORT MEMORY
    5.
    发明公开
    PSEUDO DUAL PORT MEMORY 审中-公开

    公开(公告)号：EP3350716A1

    公开(公告)日：2018-07-25

    申请号：EP16754650.6

    申请日：2016-08-16

    申请人： Qualcomm Incorporated

    发明人： KWOK, Tony Chung Yiu ,  DESAI, Nishith Nitin ,  JUNG, Changho

    IPC分类号： G06F13/16 ,  G11C7/22

    摘要： Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.