A semiconductor integrated circuit device, and a method for manufacturing a semiconductor integrated circuit device are disclosed. A first select gate electrode (DG) and a second select gate electrode (SG) are sidewall-shaped along sidewalls of a memory gate structure (4). With this configuration, the memory gate structure (4) is not disposed on the first select gate electrode (DG) and the second select gate electrode (SG). Accordingly, the memory gate structure (4), the first select gate structure (5), and the second select gate structure (6) can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer (S1) on the first select gate electrode (DG) and a silicide layer (S2) on the second select gate electrode (SG) can be separated farther from a memory gate electrode (MG) by the thickness of a cap film (CP1). Accordingly, the silicide layers (S1 and S2) on the first select gate electrode (DG) and the second select gate electrode (SG) are unlikely to contact with the memory gate electrode (MG), thereby preventing a short-circuit defect of the memory gate electrode (MG).