公开(公告)号：EP3291292A1

公开(公告)日：2018-03-07

申请号：EP16789528.3

申请日：2016-04-26

申请人： Floadia Corporation

发明人： OWADA Fukuo ,  KAWASHIMA Yasuhiko ,  YOSHIDA Shinji ,  TANIGUCHI Yasuhiro ,  OKUYAMA Kosuke

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833

摘要： A semiconductor integrated circuit device, and a method for manufacturing a semiconductor integrated circuit device are disclosed. A first select gate electrode (DG) and a second select gate electrode (SG) are sidewall-shaped along sidewalls of a memory gate structure (4). With this configuration, the memory gate structure (4) is not disposed on the first select gate electrode (DG) and the second select gate electrode (SG). Accordingly, the memory gate structure (4), the first select gate structure (5), and the second select gate structure (6) can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer (S1) on the first select gate electrode (DG) and a silicide layer (S2) on the second select gate electrode (SG) can be separated farther from a memory gate electrode (MG) by the thickness of a cap film (CP1). Accordingly, the silicide layers (S1 and S2) on the first select gate electrode (DG) and the second select gate electrode (SG) are unlikely to contact with the memory gate electrode (MG), thereby preventing a short-circuit defect of the memory gate electrode (MG).

摘要翻译： 公开了一种半导体集成电路器件以及一种用于制造半导体集成电路器件的方法。 第一选择栅极电极（DG）和第二选择栅极电极（SG）沿存储器栅极结构（4）的侧壁成侧壁形状。 利用该配置，存储栅极结构（4）不被布置在第一选择栅极电极（DG）和第二选择栅极电极（SG）上。 因此，与常规情况相比，存储栅极结构（4），第一选择栅极结构（5）和第二选择栅极结构（6）可具有相同的高度，从而实现尺寸的减小。 此外，第一选择栅极电极（DG）上的硅化物层（S1）和第二选择栅极电极（SG）上的硅化物层（S2）可以远离存储器栅极电极（MG）分开厚度 一个盖膜（CP1）。 因此，第一选择栅极电极（DG）和第二选择栅极电极（SG）上的硅化物层（S1和S2）不可能与存储器栅极电极（MG）接触，由此防止 存储器栅电极（MG）。

公开(公告)号：EP3264464A1

公开(公告)日：2018-01-03

申请号：EP16755350.2

申请日：2016-02-19

申请人： Floadia Corporation

发明人： KASAI Hideo ,  TANIGUCHI Yasuhiro ,  KAWASHIMA Yasuhiko ,  SAKURAI Ryotaro ,  SHINAGAWA Yutaka ,  TOYA Tatsuro ,  YAMAGUCHI Takanori ,  OWADA Fukuo ,  YOSHIDA Shinji ,  HATADA Teruo ,  NODA Satoshi ,  KATO Takafumi ,  MURAYA Tetsuya ,  OKUYAMA Kosuke

IPC分类号： H01L27/10

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252

摘要： In a semiconductor memory device (1), voltage application from a memory gate electrode (G) of the memory capacitor (4) to a word line can be blocked by a rectifier element (3) depending on values of voltages applied to the memory gate electrode (G) and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device (1), for example, each bit line contact (BC15) is shared by four anti-fuse memories (2a 6 , 2a 7 , 2a 10 , and 2a 11 ) adjacent to each other and each word line contact (WC12) is shared by four anti-fuse memories (2a 3 , 2a 4 , 2a 7 , and 2a 8 ) adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

摘要翻译： 在半导体存储器件（1）中，从存储电容器（4）的存储器栅电极（G）到字线的电压施加可以由整流器元件（3）根据施加到存储器栅极 电极（G）和字线而不使用传统的控制电路。 该配置消除了与传统情况中一样提供用于导通和关断开关晶体管的开关晶体管和开关控制电路的需要，并且相应地实现了小型化。 在半导体存储器件（1）中，例如，每个位线触点（BC15）由彼此相邻的四个反熔丝存储器（2a6,2a7,2a10和2a11）共享，并且每个字线触点（WC12）是 由彼此相邻的四个反熔丝存储器（2a3,2a4,2a7和2a8）共享，从而与其中位线接触件和字线接触件分别提供给每个反熔丝存储件的情况相比，由此实现了整个设备的小型化 反熔丝内存。

公开(公告)号：EP3355354A1

公开(公告)日：2018-08-01

申请号：EP17785850.3

申请日：2017-04-11

申请人： Floadia Corporation

发明人： NODA Satoshi ,  TANIGUCHI Yasuhiro ,  KASAI Hideo ,  KATO Takafumi ,  KAWASHIMA Yasuhiko ,  OWADA Fukuo

IPC分类号： H01L27/11573 ,  H01L21/336 ,  H01L21/822 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/822 ,  H01L27/04 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

摘要： In a non-volatile semiconductor memory device (1) according to the present invention, a capacitive sidewall insulating film (21) of a capacitive element (C1, C2) is made of a layer same as that of a sidewall spacer (13a, 13b) of a memory cell (2), the film qualities and thicknesses of which are adjusted mainly for breakdown voltage. The configuration leads to an improved breakdown voltage characteristic and a stabilized capacitor characteristic of the capacitive element (C1, C2). The non-volatile semiconductor memory device (1) does not need a conventionally needed power supply for achieving low voltage application to a capacitive element, thereby achieving a simplified and downsized configuration accordingly.

公开(公告)号：EP3293756A1

公开(公告)日：2018-03-14

申请号：EP16875485.1

申请日：2016-12-07

申请人： Floadia Corporation

发明人： OKADA Daisuke ,  YANAGISAWA Kazumasa ,  OWADA Fukuo ,  YOSHIDA Shoji ,  KAWASHIMA Yasuhiko ,  YOSHIDA Shinji ,  TANIGUCHI Yasuhiro ,  OKUYAMA Kosuke

IPC分类号： H01L21/336 ,  G11C16/02 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/788 ,  H01L29/792

摘要： When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

摘要翻译： 当通过减小在鳍片（S2）内具有高杂质浓度的鳍片（S2）的表面上的漏极区域（12a）和源极区域（12b）之间的距离来缩小存储器单元（MC） （S2）的位置可以被设置为使得存储器栅极电极（MG）和鳍片（S2）之间的电位差减小以抑制干扰的发生。 因此，存储单元（MC）实现了小型化和抑制干扰的发生。

公开(公告)号：EP3300111A1

公开(公告)日：2018-03-28

申请号：EP16827814.1

申请日：2016-07-21

申请人： Floadia Corporation

发明人： YOSHIDA Shoji ,  OWADA Fukuo ,  OKADA Daisuke ,  KAWASHIMA Yasuhiko ,  YOSHIDA Shinji ,  YANAGISAWA Kazumasa ,  TANIGUCHI Yasuhiro

IPC分类号： H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L21/28 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

摘要： A memory cell according to the present invention (1) includes a memory gate structure (2), a first select gate structure (3), and a second select gate structure (4). In the memory gate structure (2), a lower memory gate insulating film (10), a charge storage layer (EC), an upper memory gate insulating film (11), and a metal memory gate electrode (MG) are stacked in this order. The first select gate structure (3) includes a metal first select gate electrode (DG) along a first sidewall spacer (8a) provided on a sidewall of the memory gate structure (2). The second select gate structure (4) includes a metal second select gate electrode (SG) along a second sidewall spacer (8b) provided on another sidewall of the memory gate structure (2). With this configuration, the metal memory gate electrode (MG), the metal first select gate electrode (DG), and the metal second select gate electrode (SG) can be formed of a metallic material the same as that of a metal logic gate electrode (LG11). Thus, the memory cell can be formed through a series of manufacturing processes of forming the metal logic gate electrode (LG1) made of a metallic material on a semiconductor substrate.

摘要翻译： 根据本发明的存储器单元（1）包括存储器栅极结构（2），第一选择栅极结构（3）和第二选择栅极结构（4）。 在存储器栅极结构（2）中，在其中堆叠下部存储器栅极绝缘膜（10），电荷存储层（EC），上部存储器栅极绝缘膜（11）和金属存储器栅极电极（MG） 订购。 第一选择栅极结构（3）包括沿着设置在存储器栅极结构（2）的侧壁上的第一侧壁间隔物（8a）的金属第一选择栅极电极（DG）。 第二选择栅极结构（4）包括沿着设置在存储器栅极结构（2）的另一侧壁上的第二侧壁间隔物（8b）的金属第二选择栅极电极（SG）。 利用该配置，金属存储器栅极电极（MG），金属第一选择栅极电极（DG）和金属第二选择栅极电极（SG）可以由与金属逻辑栅极电极 （LG11）。 因此，可以通过在半导体衬底上形成由金属材料制成的金属逻辑栅电极（LG1）的一系列制造工艺来形成存储器单元。

公开(公告)号：EP3300103A1

公开(公告)日：2018-03-28

申请号：EP16803262.1

申请日：2016-05-27

申请人： Floadia Corporation

发明人： TANIGUCHI Yasuhiro ,  OWADA Fukuo ,  KAWASHIMA Yasuhiko ,  YOSHIDA Shinji ,  OKUYAMA Kosuke

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/408 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

摘要： A memory cell and a non-volatile semiconductor memory device are disclosed. Nitride sidewall layers (32a and 32b) are respectively disposed in a first sidewall spacer (28a) and a second sidewall spacer (28b), to separate a memory gate electrode (MG) and a first select gate electrode (DG) from each other and the memory gate electrode (MG) and a second select gate electrode (SG) from each other. Hence, a breakdown voltage is improved around the memory gate electrode (MG) as compared with a conventional case in which the first sidewall spacer (28a) and the second sidewall spacer (28b) are simply made of insulating oxide films. The nitride sidewall layers (32a and 32b) are disposed farther from a memory well (MW) than a charge storage layer (EC). Hence, charge is unlikely to be injected into the nitride sidewall layers (32a and 32b) at charge injection from the memory well (MW) into the charge storage layer (EC), thereby preventing an operation failure due to charge storage in a region other than the charge storage layer (EC).

摘要翻译： 公开了一种存储单元和非易失性半导体存储器件。 氮化物侧壁层（32a和32b）分别设置在第一侧壁间隔物（28a）和第二侧壁间隔物（28b）中，以将存储器栅极电极（MG）和第一选择栅极电极（DG）彼此分隔开并且 存储器栅极电极（MG）和第二选择栅极电极（SG）。 因此，与其中第一侧壁间隔物（28a）和第二侧壁间隔物（28b）仅由绝缘氧化物膜制成的传统情况相比，存储器栅极电极（MG）周围的击穿电压得到改善。 氮化物侧壁层（32a和32b）比电荷存储层（EC）更远离存储阱（MW）设置。 因此，在从存储器阱（MW）向电荷存储层（EC）注入电荷时，电荷不可能注入到氮化物侧壁层（32a和32b）中，由此防止由于其他区域中的电荷存储而导致的操作故障 比电荷存储层（EC）。

公开(公告)号：EP3316282A1

公开(公告)日：2018-05-02

申请号：EP16834972.8

申请日：2016-07-26

申请人： Floadia Corporation

发明人： OWADA Fukuo ,  TANIGUCHI Yasuhiro ,  KAWASHIMA Yasuhiko ,  YOSHIDA Shinji ,  KASAI Hideo ,  SAKURAI Ryotaro ,  SHINAGAWA Yutaka ,  OKUYAMA Kosuke

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L21/823456 ,  H01L27/092 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/42344

摘要： A method for producing semiconductor integrated circuit devices and a semiconductor integrated circuit device produced by the method are provided. In the method, when a first select gate electrode (G2a, G2b) and a second select gate electrode (G3a, G3b) that are independently controllable are formed in a production process, an extra dedicated photomask process for electrically separating the first select gate electrode (G2a, G2b) and the second select gate electrode (G3a, G3b) is not needed in addition to a conventional dedicated photomask process of fabricating a memory circuit region only, thereby achieving reduction in a production cost accordingly.

摘要翻译： 提供了一种用于制造半导体集成电路器件的方法以及由该方法制造的半导体集成电路器件。 在该方法中，当在制造工艺中形成可独立控制的第一选择栅极电极（G2a，G2b）和第二选择栅极电极（G3a，G3b）时，用于电分离第一选择栅极电极的额外专用光掩模工艺 （G2a，G2b）和第二选择栅极电极（G3a，G3b），除了仅制造存储器电路区域的传统专用光掩模工艺之外，因此实现了生产成本的降低。