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    NON-VOLATILE SRAM MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
    2.
    发明公开
    NON-VOLATILE SRAM MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
    非易失性SRAM存储器单元和非易失性半导体存储器件

    公开(公告)号：EP3276654A1

    公开(公告)日：2018-01-31

    申请号：EP16772411.1

    申请日：2016-03-18

    申请人： Floadia Corporation

    发明人： SHINAGAWA Yutaka ,  TANIGUCHI Yasuhiro ,  KASAI Hideo ,  SAKURAI Ryotaro ,  KAWASHIMA Yasuhiko ,  TOYA Tatsuro ,  OKUYAMA Kosuke

    IPC分类号： H01L21/8244 ,  G11C14/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C14/0063 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/1116 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

    摘要： A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM (15) to a non-volatile memory unit (16) through fast operation of the SRAM (15) are disclosed. A non-volatile semiconductor memory device (1) can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit (16). Thus, a first access transistor (21 a), a second access transistor (21 b), a first load transistor (22a), a second load transistor (22b), a first drive transistor (23a), and a second drive transistor (23b) included in the SRAM (15) connected with the non-volatile memory unit (16) can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM (15) at a lower power supply voltage.

    摘要翻译： 公开了一种能够通过SRAM（15）的快速操作将SRAM中的SRAM数据编程到非易失性存储器单元（16）的非易失性SRAM存储器单元和非易失性半导体存储器件。 非易失性半导体存储器件（1）可以实现编程操作所需的电压的降低，以将SRAM数据编程到非易失性存储器单元（16）。 因此，第一存取晶体管（21a），第二存取晶体管（21b），第一负载晶体管（22a），第二负载晶体管（22b），第一驱动晶体管（23a）和第二驱动晶体管（ 23b）包括在与非易失性存储单元（16）连接的SRAM（15）中的每一个都可以包括具有小于或等于4nm的厚度的栅极绝缘膜，其实现SRAM（15）在 降低电源电压。

    MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
    3.
    发明公开
    MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
    存储器单元和非易失性半导体存储器件

    公开(公告)号：EP3232465A1

    公开(公告)日：2017-10-18

    申请号：EP15851362.2

    申请日：2015-10-06

    申请人： Floadia Corporation

    发明人： SHINAGAWA Yutaka ,  TANIGUCHI Yasuhiro ,  KASAI Hideo ,  SAKURAI Ryotaro ,  KAWASHIMA Yasuhiko ,  TOYA Tatsuro ,  OKUYAMA Kosuke

    IPC分类号： H01L21/336 ,  G11C16/02 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/788 ,  G11C11/34 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  H01L27/115 ,  H01L28/00 ,  H01L29/792 ,  H01L45/04

    摘要： A voltage applied to a bit line (BL1) or a voltage applied to a source line (SL) is reduced to a value that allows a first select gate structure (5) or a second select gate structure (6) to block electrical connection between the bit line (BL1) and a channel layer (CH) or between the source line (SL) and the channel layer (CH), irrespective of a charge storage gate voltage needed to inject charge into a charge storage layer (EC) by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a first select gate insulating film (30) of the first select gate structure (5) and thickness of a second select gate insulating film (33) of the second select gate structure (6) are reduced. High-speed operation is achieved correspondingly. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a gate insulating film of a field effect transistor in a peripheral circuit that controls a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.

    摘要翻译： 施加到位线（BL1）的电压或施加到源极线（SL）的电压降低到允许第一选择栅极结构（5）或第二选择栅极结构（6）阻止 位线（BL1）和沟道层（CH）之间或源极线（SL）和沟道层（CH）之间的电荷存储栅极电压，而不考虑将电荷注入电荷存储层 量子隧道效应。 根据施加到位线（BL1）和源极线（SL）的电压的减少，第一选择栅极结构（5）的第一选择栅极绝缘膜（30）的厚度和 减少第二选择栅极结构（6）的第二选择栅极绝缘膜（33）。 高速运转也相应实现。 根据施加到位线（BL1）和源极线（SL）的电压的减少，控制存储器单元的外围电路中的场效应晶体管的栅极绝缘膜的厚度减小。 外围电路的面积相应减小。

    MEMORY CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    10.
    发明公开
    MEMORY CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    存储器单元，半导体集成电路装置及制造半导体集成电路装置的方法

    公开(公告)号：EP3300111A1

    公开(公告)日：2018-03-28

    申请号：EP16827814.1

    申请日：2016-07-21

    申请人： Floadia Corporation

    发明人： YOSHIDA Shoji ,  OWADA Fukuo ,  OKADA Daisuke ,  KAWASHIMA Yasuhiko ,  YOSHIDA Shinji ,  YANAGISAWA Kazumasa ,  TANIGUCHI Yasuhiro

    IPC分类号： H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/115 ,  H01L21/28 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

    摘要： A memory cell according to the present invention (1) includes a memory gate structure (2), a first select gate structure (3), and a second select gate structure (4). In the memory gate structure (2), a lower memory gate insulating film (10), a charge storage layer (EC), an upper memory gate insulating film (11), and a metal memory gate electrode (MG) are stacked in this order. The first select gate structure (3) includes a metal first select gate electrode (DG) along a first sidewall spacer (8a) provided on a sidewall of the memory gate structure (2). The second select gate structure (4) includes a metal second select gate electrode (SG) along a second sidewall spacer (8b) provided on another sidewall of the memory gate structure (2). With this configuration, the metal memory gate electrode (MG), the metal first select gate electrode (DG), and the metal second select gate electrode (SG) can be formed of a metallic material the same as that of a metal logic gate electrode (LG11). Thus, the memory cell can be formed through a series of manufacturing processes of forming the metal logic gate electrode (LG1) made of a metallic material on a semiconductor substrate.

    摘要翻译： 根据本发明的存储器单元（1）包括存储器栅极结构（2），第一选择栅极结构（3）和第二选择栅极结构（4）。 在存储器栅极结构（2）中，在其中堆叠下部存储器栅极绝缘膜（10），电荷存储层（EC），上部存储器栅极绝缘膜（11）和金属存储器栅极电极（MG） 订购。 第一选择栅极结构（3）包括沿着设置在存储器栅极结构（2）的侧壁上的第一侧壁间隔物（8a）的金属第一选择栅极电极（DG）。 第二选择栅极结构（4）包括沿着设置在存储器栅极结构（2）的另一侧壁上的第二侧壁间隔物（8b）的金属第二选择栅极电极（SG）。 利用该配置，金属存储器栅极电极（MG），金属第一选择栅极电极（DG）和金属第二选择栅极电极（SG）可以由与金属逻辑栅极电极 （LG11）。 因此，可以通过在半导体衬底上形成由金属材料制成的金属逻辑栅电极（LG1）的一系列制造工艺来形成存储器单元。