Invention Publication
- Patent Title: APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
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Application No.: EP20173833.3Application Date: 2011-09-30
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Publication No.: EP3712774A1Publication Date: 2020-09-23
- Inventor: RAMANUJAN, Raj K. , AGARWAL, Rajat , CHENG, Kai , POLEPEDDI, Taarinya , RAAD, Camille C. , ZIMMERMAN, David J. , SWAMINATHAN, Muthukumar P. , ZIAKAS, Dimitrios , KUMAR, Mohan J. , COURY, Bassam N. , HINTON, Glenn J.
- Applicant: INTEL Corporation
- Applicant Address: 2200 Mission College Blvd. Santa Clara, CA 95054 US
- Assignee: INTEL Corporation
- Current Assignee: INTEL Corporation
- Current Assignee Address: 2200 Mission College Blvd. Santa Clara, CA 95054 US
- Agency: Rummler, Felix
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G11C7/10 ; G06F12/08
Abstract:
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."
Public/Granted literature
- EP3712774B1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY Public/Granted day:2023-02-15
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