公开(公告)号：EP4104049A1

公开(公告)日：2022-12-21

申请号：EP20918730.1

申请日：2020-12-22

Applicant: INTEL Corporation

Inventor： JAYAKUMAR, Sarathy ,  KUMAR, Mohan J. ,  NACHIMUTHU, Murugasamy K. ,  ROTHMAN, Michael A.

IPC: G06F8/656 ,  G06F21/57 ,  G06F9/4401

公开(公告)号：EP4012553A1

公开(公告)日：2022-06-15

申请号：EP21198375.4

申请日：2021-09-22

Applicant: INTEL Corporation

Inventor： JAYAKUMAR, Sarathy ,  SONG, Chuan ,  KUMAR, Mohan J.

IPC: G06F8/656 ,  G06F9/48 ,  G06F12/06 ,  G06F12/14

Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. Under the uCode hot-upgrade method, a uCode path is received at an out-of-band controller ( e.g. , baseboard management controller (BMC)) and buffered in a memory buffer in the out-of-band controller. The out-of-band controller exposes the memory buffer as a Memory-Mapped Input-Output (MMIO) range to a host CPU. A uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for live-patch without touching the tenant operating system environment.

公开(公告)号：EP3761177A1

公开(公告)日：2021-01-06

申请号：EP20164715.3

申请日：2020-03-20

Applicant: INTEL Corporation

Inventor： GANGULI, Mrittika ,  NACHIMUTHU, Murugasamy K. ,  SUNDARARAJAN, Muralidharan ,  BALLE, Susanne M. ,  KUMAR, Mohan J.

IPC: G06F9/50 ,  H04L12/24 ,  H04L12/26

Abstract: Technologies for providing latency-aware consensus management in a disaggregated system include a compute device. The compute device includes circuitry to determine latencies associated with subsystems of the disaggregated system. Additionally, the circuitry is to determine, as a function of the determined latencies, a time period in which a configuration change to the disaggregated system is to reach a consistent state in the subsystems.

公开(公告)号：EP2972852B1

公开(公告)日：2020-07-15

申请号：EP14774197.9

申请日：2014-02-26

Applicant: Intel Corporation

Inventor： JAYAKUMAR, Sarathy ,  KUMAR, Mohan J. ,  KINNEY, Michael D.

IPC: G06F9/48 ,  G06F9/38 ,  G06F11/07

公开(公告)号：EP3588307A1

公开(公告)日：2020-01-01

申请号：EP19176600.5

申请日：2019-05-24

Applicant: INTEL Corporation

Inventor： NACHIMUTHU, Murugasamy K. ,  SCHMISSEUR, Mark A. ,  ZIAKAS, Dimitrios ,  DAS SHARMA, Debendra ,  KUMAR, Mohan J.

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/40 ,  G06F13/16

Abstract: An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.

公开(公告)号：EP3382500A1

公开(公告)日：2018-10-03

申请号：EP18154432.1

申请日：2018-01-31

Applicant: Intel Corporation

Inventor： KUMAR, Mohan J. ,  NACHIMUTHU, Murugasamy K. ,  SRINIVASAN, Vasudevan

IPC: G06F1/20 ,  G06F1/30 ,  G06F11/30 ,  G06F1/32 ,  G06F1/28

CPC classification number: H04L47/2425 ,  G06F1/206 ,  G06F1/28 ,  G06F1/30 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/5044 ,  G06F9/5094 ,  G06F11/3058 ,  H04L41/5022 ,  H04L47/805 ,  H04L67/1008 ,  H04L67/12 ,  Y02D10/126 ,  Y02D10/172

Abstract: A rack system including a plurality of nodes can implement thermal/power throttling, sub-node composition, and processing balancing based on voltage/frequency. In the thermal/power throttling, at least one resource is throttled, based at least in part on a heat event or a power event. In the sub-node composition, a plurality of computing cores is divided into a target number of domains. In the processing balancing based on voltage/frequency, a first core performs a first processing job at a first voltage or frequency, and a second core performs a second processing job at a second voltage or frequency different from the first voltage or frequency.

公开(公告)号：EP3910469A1

公开(公告)日：2021-11-17

申请号：EP20214390.5

申请日：2020-12-15

Applicant: INTEL Corporation

Inventor： NACHIMUTHU, Murugasamy ,  GANDIGA SHIVAKUMUR, Deepak ,  WILLIAMS, Dan ,  KASANICKY, Tiffany ,  RUSOCKI, Krzysztof ,  MOULIN, Nicholas ,  KUMAR, Mohan J.

IPC: G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F9/4401

Abstract: Apparatus and computer readable storage medium comprising a set of executable program instructions may provide for technology that exchanges activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information. The technology also conducts a runtime upgrade of a device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system.

公开(公告)号：EP3877854A1

公开(公告)日：2021-09-15

申请号：EP19882848.5

申请日：2019-04-16

Applicant: INTEL Corporation

Inventor： HAGHIGHAT, Mohammad R. ,  DOSHI, Kshitij ,  HERDRICH, Andrew J. ,  MOHAN, Anup ,  IYER, Ravishankar R. ,  SUN, Mingqiu ,  BHUYAN, Krishna ,  GOH, Teck Joo ,  KUMAR, Mohan J. ,  PRINKE, Michael ,  LEMAY, Michael ,  PELED, Leeor ,  TSAI, Jr-Shian ,  DURHAM, David M. ,  CHAMBERLAIN, Jeffrey D. ,  SUKHOMLINOV, Vadim A. ,  DAHLEN, Eric J. ,  BAGHSORKHI, Sara ,  SANE, Harshad ,  MELIK-ADAMYAN, Areg ,  SAHITA, Ravi ,  BABOKIN, Dmitry Yurievich ,  STEINER, Ian M. ,  BACHMUTSKY, Alexander ,  RAO, Anil ,  ZHANG, Mingwei ,  JAIN, Nilesh K. ,  FIROOZSHAHIAN, Amin ,  PATEL, Baiju V. ,  HUANG, Wenyong ,  RAGHURAM, Yeluri

IPC: G06F9/50 ,  G06F11/30

公开(公告)号：EP3712774A1

公开(公告)日：2020-09-23

申请号：EP20173833.3

申请日：2011-09-30

Applicant: INTEL Corporation

Inventor： RAMANUJAN, Raj K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille C. ,  ZIMMERMAN, David J. ,  SWAMINATHAN, Muthukumar P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan J. ,  COURY, Bassam N. ,  HINTON, Glenn J.

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/08

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."

公开(公告)号：EP3343374A2

公开(公告)日：2018-07-04

申请号：EP17204240.0

申请日：2017-11-28

Applicant: INTEL Corporation

Inventor： JAYAKUMAR, Sarathy ,  KUMAR, Mohan J. ,  RAJ, Ashok ,  GURUMOORTHY, Hemalatha ,  STORY, Ronald N.

IPC: G06F11/16 ,  G06F11/20

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1666 ,  G06F11/2056 ,  G06F11/2094

Abstract: A systems and methods for dynamic address based mirroring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.