An apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link. The transition to active power state comprises a wake-up pulse sequence (410), a PHY link establishment signal pattern (420) and a clock and data switch CDS signal pattern (430) followed by the video signal. The CDS enables the LTTPR to be trained so as to obtain a seamless communication between the DP-TX and the DP-RX.