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    ADVANCED LINK POWER MANAGEMENT FOR DISPLAYPORT
    1.
    发明公开
    ADVANCED LINK POWER MANAGEMENT FOR DISPLAYPORT 审中-公开

    公开(公告)号：EP4016520A1

    公开(公告)日：2022-06-22

    申请号：EP21198428.1

    申请日：2021-09-23

    申请人： INTEL Corporation

    发明人： ANSARI, Nausheen ,  KABIRY, Ziv ,  YEDIDIA, Gal

    IPC分类号： G09G5/00 ,  G06F1/3234

    摘要： An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.

    DISPLAY LINK POWER MANAGEMENT USING IN-BAND LOW-FREQUENCY PERIODIC SIGNALING
    4.
    发明公开
    DISPLAY LINK POWER MANAGEMENT USING IN-BAND LOW-FREQUENCY PERIODIC SIGNALING 审中-公开

    公开(公告)号：EP4016519A1

    公开(公告)日：2022-06-22

    申请号：EP21197824.2

    申请日：2021-09-20

    申请人： INTEL Corporation

    发明人： ANSARI, Nausheen ,  KABIRY, Ziv ,  YEDIDIA, Gal

    IPC分类号： G09G5/00 ,  G06F13/42

    摘要： An apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link. The transition to active power state comprises a wake-up pulse sequence (410), a PHY link establishment signal pattern (420) and a clock and data switch CDS signal pattern (430) followed by the video signal. The CDS enables the LTTPR to be trained so as to obtain a seamless communication between the DP-TX and the DP-RX.

    LINK BANDWIDTH IMPROVEMENT TECHNIQUES
    8.
    发明公开
    LINK BANDWIDTH IMPROVEMENT TECHNIQUES 审中-公开

    公开(公告)号：EP4036702A1

    公开(公告)日：2022-08-03

    申请号：EP21212844.1

    申请日：2020-03-27

    申请人： INTEL Corporation

    发明人： ANSARI, Nausheen ,  KABIRY, Ziv

    IPC分类号： G06F3/14 ,  H04N21/4363 ,  G09G5/00

    摘要： One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

    COMBINED PANEL SELF-REFRESH (PSR) AND ADAPTIVE SYNCHRONIZATION SYSTEMS AND METHODS
    9.
    发明公开
    COMBINED PANEL SELF-REFRESH (PSR) AND ADAPTIVE SYNCHRONIZATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：EP4002345A1

    公开(公告)日：2022-05-25

    申请号：EP21217055.9

    申请日：2020-03-20

    申请人： Intel Corporation

    发明人： ANSARI, Nausheen ,  SMITH, Gary

    IPC分类号： G09G5/00 ,  G06F1/32

    摘要： The present disclosure is directed to systems and methods of maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device. To maintain synchronization, in some instances the source device and the sink device may maintain synchronization contemporaneous with at least a portion of the PSR/PSR2 operating mode. To maintain synchronization, in some instances, a high-bandwidth communications link may be maintained between the source device and the sink device. In some instances, synchronization between the source device and the sink device may be interrupted upon the source device entering the PSR/PSR2 operating mode and may be re-established upon the source device exiting the PSR/PSR2 operating mode.

    DISPLAY PANEL SYNCHRONIZATION FOR A DISPLAY DEVICE
    10.
    发明公开
    DISPLAY PANEL SYNCHRONIZATION FOR A DISPLAY DEVICE 审中-公开

    公开(公告)号：EP3550422A1

    公开(公告)日：2019-10-09

    申请号：EP19160419.8

    申请日：2019-03-01

    申请人： INTEL Corporation

    发明人： ANSARI, Nausheen ,  SUZUKI, Nobuyuki ,  ZHUANG, Zhiming

    IPC分类号： G06F3/14 ,  G09G5/00 ,  G09G5/12

    摘要： Technology for a display device is described. The display device can include one or more display screens operable to show at least two display panels. The display device can include a controller. The controller can send a request for frame data from each of the at least two display panels to a source device. The controller can receive, from the source device, a same frame indication for each of the at least two display panels. The controller can provide frame data received from the source device based on the same frame indication to the at least two display panels. The same frame indication can cause the at least two display panels to synchronously display frame data received from the source device.