公开(公告)号：EP4016519A1

公开(公告)日：2022-06-22

申请号：EP21197824.2

申请日：2021-09-20

申请人： INTEL Corporation

发明人： ANSARI, Nausheen ,  KABIRY, Ziv ,  YEDIDIA, Gal

IPC分类号： G09G5/00 ,  G06F13/42

摘要： An apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link. The transition to active power state comprises a wake-up pulse sequence (410), a PHY link establishment signal pattern (420) and a clock and data switch CDS signal pattern (430) followed by the video signal. The CDS enables the LTTPR to be trained so as to obtain a seamless communication between the DP-TX and the DP-RX.

公开(公告)号：EP4016520A1

公开(公告)日：2022-06-22

申请号：EP21198428.1

申请日：2021-09-23

申请人： INTEL Corporation

发明人： ANSARI, Nausheen ,  KABIRY, Ziv ,  YEDIDIA, Gal

IPC分类号： G09G5/00 ,  G06F1/3234

摘要： An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.