- 专利标题: LOW GERMANIUM, HIGH BORON SILICON RICH CAPPING LAYER FOR PMOS CONTACT RESISTANCE THERMAL STABILITY
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申请号: EP22180459.4申请日: 2022-06-22
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公开(公告)号: EP4109553A1公开(公告)日: 2022-12-28
- 发明人: NANDI, Debaleena , BOMBERGER, Cory , DEWEY, Gilbert , MURTHY, Anand S. , KOBRINSKY, Mauro , SHAH, Rushabh , CHOI, Chi-Hing , KENNEL, Harold W. , SAADAT, Omair , ONI, Adedapo , HARATIPOUR, Nazila , GHANI, Tahir
- 申请人: INTEL Corporation
- 申请人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 代理机构: 2SPL Patentanwälte PartG mbB
- 优先权: US202117359327 20210625
- 主分类号: H01L29/417
- IPC分类号: H01L29/417 ; H01L29/08 ; H01L29/66 ; H01L29/78
摘要:
Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.
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