公开(公告)号：EP4203063A1

公开(公告)日：2023-06-28

申请号：EP22213210.2

申请日：2022-12-13

申请人： INTEL Corporation

发明人： HARATIPOUR, Nazila ,  DEWEY, Gilbert ,  TUNG, I-Cheng ,  ZELICK, Nancy ,  CHOI, Chi-Hing ,  JHA, Jitendra Kumar ,  KAVALIEROS, Jack T.

IPC分类号： H01L29/417 ,  H01L29/45

摘要： Contact over active gate (COAG) structures with trench contact layers, and methods of fabricating contact over active gate (COAG) structures using trench contact layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is adjacent to the gate structure. A conductive trench contact structure is on the epitaxial source or drain structure. The conductive trench contact structure includes a first planar layer on the epitaxial source or drain structure, a second planar layer on the first planar layer, and a conductive fill material on the second planar layer.

公开(公告)号：EP4199062A1

公开(公告)日：2023-06-21

申请号：EP22206578.1

申请日：2022-11-10

申请人： INTEL Corporation

发明人： RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  AGRAWAL, Ashish ,  MORROW, Patrick ,  SUNG, Seung Hoon ,  HUANG, Cheng-Ying ,  THOMAS, Nicole ,  HARATIPOUR, Nazila

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L27/092 ,  H01L21/8238

摘要： Techniques are provided herein to form semiconductor devices having a non-reactive metal contact in an epi region of a stacked transistor configuration. An n-channel device may be located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel and the p-channel, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A deep and narrow contact is formed from either the frontside or the backside of the integrated circuit through the stacked source or drain regions. According to some embodiments, the contact is formed using a refractory metal or other non-reactive metal such that no silicide or germanide is formed with the epi material of the source or drain regions at the boundary between the contact and the source or drain regions.

公开(公告)号：EP4020562A1

公开(公告)日：2022-06-29

申请号：EP21209878.4

申请日：2021-11-23

申请人： INTEL Corporation

发明人： HARATIPOUR, Nazila ,  CHANG, Sou-Chi ,  SHIVARAMAN, Shriram ,  PECK, Jason ,  AVCI, Uygar, E. ,  KAVALIEROS, Jack T.

IPC分类号： H01L27/11514 ,  H01L27/24

摘要： A memory device comprises a series of alternating plate lines and an insulating material over a substrate. Two or more ferroelectric capacitors are through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel wordlines is along a second direction orthogonal to the first direction over the two or more ferroelectric capacitors. An access transistor is located over and controls the two or more ferroelectric capacitors, the access transistor incorporating a first one of the bitlines and a first one of the wordlines. The bitline comprise a first source/drain of a source/drain pair, and a second source/drain is aligned, and in contact, with a top one of the two or more ferroelectric capacitors, and the first wordline forms a gate of the access transistor.

公开(公告)号：EP3706167A1

公开(公告)日：2020-09-09

申请号：EP20153095.3

申请日：2020-01-22

申请人： INTEL Corporation

发明人： LIN, Chia-Ching ,  CHANG, Sou-Chi ,  PENUMATCHA, Ashish Verma ,  HARATIPOUR, Nazila ,  SUNG, Seung Hoon ,  LOH, Owen Y. ,  KAVALIEROS, Jack ,  AVCI, Uygar E. ,  YOUNG, Ian A.

IPC分类号： H01L27/11507 ,  H01L49/02 ,  H01G4/005 ,  H01G4/33

摘要： Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.

公开(公告)号：EP4202977A1

公开(公告)日：2023-06-28

申请号：EP22214363.8

申请日：2022-12-16

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  DEWEY, Gilbert ,  GHANI, Tahir ,  HARATIPOUR, Nazila ,  KOBRINSKY, Mauro J. ,  MURTHY, Anand

IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L21/768

摘要： The formation of titanium contacts to silicon germanium (SiGe) comprises the formation of a titanium silicide layer in which the silicon for the titanium silicide layer is provided by flowing silane (disilane, trisilane, etc.) over a titanium layer at an elevated temperature. The titanium silicide layer can help limit the amount of titanium and germanium interdiffusion that can occur across the titanium silicide-silicon germanium interface, which can reduce (or eliminate) the formation of voids in the SiGe layer during subsequent anneal and other high-temperature processes. The surface of the SiGe layer upon which the titanium layer is formed can also be preamorphized via boron and germanium implantation to further improve the robustness of the SiGe layer against microvoid development. The resulting titanium contacts are thermally stable in that their resistance remains substantially unchanged after being subjected to downstream annealing and high-temperature processing processes.

公开(公告)号：EP4195289A1

公开(公告)日：2023-06-14

申请号：EP22204877.9

申请日：2022-11-01

申请人： INTEL Corporation

发明人： SEN GUPTA, Arnab ,  DEWEY, Gilbert ,  CHOUKSEY, Siddharth ,  HARATIPOUR, Nazila ,  KAVALIEROS, Jack ,  METZ, Mathew ,  CLENDENNING, Scott ,  RETASKET, Jason ,  JOHNSON, Edward

IPC分类号： H01L29/45 ,  H01L29/417 ,  H01L29/78

摘要： Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

公开(公告)号：EP4016625A1

公开(公告)日：2022-06-22

申请号：EP21194830.2

申请日：2021-09-03

申请人： INTEL Corporation

发明人： Shivaraman, Shriram ,  AVCI, Uygar E. ,  Chang, Sou-Chi ,  HARATIPOUR, Nazila ,  KAVALIEROS, Jack

IPC分类号： H01L27/11514

摘要： Plate line architectures for 3D-Ferroelectric Random Access Memory (3D-FRAM) are described. In an example, a memory device includes a plurality of bitlines (108) along a first direction and a plurality of wordlines (110) along a second direction orthogonal to the first direction. An access transistor (106) is at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines (PL1, ..., PL4) and insulating material (118) are fabricated over the access transistor. Two or more ferroelectric capacitors (102) are over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor.

公开(公告)号：EP3975262A1

公开(公告)日：2022-03-30

申请号：EP21192890.8

申请日：2021-08-24

申请人： INTEL Corporation

发明人： DEWEY, Gilbert ,  HARATIPOUR, Nazila ,  CHOUKSEY, Siddharth ,  SEN GUPTA, Arnab ,  JEZEWSKI, Christopher ,  TUNG, I-Cheng ,  METZ, Matthew V. ,  MURTHY, Anand S.

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L27/088 ,  H01L29/40 ,  H01L29/45 ,  H01L21/336 ,  H01L29/417 ,  H01L21/8234 ,  B82Y10/00

摘要： Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

公开(公告)号：EP3832735A2

公开(公告)日：2021-06-09

申请号：EP20198182.6

申请日：2020-09-24

申请人： INTEL Corporation

发明人： SUNG, Seung Hoon ,  PENUMATCHA, Ashish Verma ,  CHANG, Sou-Chi ,  MERRILL, Devin ,  TUNG, I-Cheng ,  HARATIPOUR, Nazila ,  KAVALIEROS, Jack ,  YOUNG, Ian ,  METZ, Matthew ,  AVCI, Uygar ,  LIN, Chia-Ching ,  LOH, Owen ,  SHIVARAMAN, Shriram ,  MATTSON, Eric

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/51

摘要： A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：EP3716300A1

公开(公告)日：2020-09-30

申请号：EP20163971.3

申请日：2020-03-18

申请人： INTEL Corporation

发明人： HARATIPOUR, Nazila ,  LIN, Chia-Ching ,  CHANG, Sou-Chi ,  PENUMATCHA, Ashish Verma ,  LOH, Owen ,  LU, Mengcheng ,  SUNG, Seung Hoon ,  YOUNG, Ian A. ,  AVCI, Uygar ,  KAVALIEROS, Jack T.

IPC分类号： H01G4/008 ,  H01G4/08 ,  H01G4/012 ,  H01G4/228 ,  H01G4/236 ,  H01G4/33 ,  H01L21/00 ,  H01L49/02

摘要： A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.