公开(公告)号：EP4156281A1

公开(公告)日：2023-03-29

申请号：EP22185002.7

申请日：2022-07-14

申请人： Intel Corporation

发明人： NANDI, Debaleena ,  KOBRINSKY, Mauro J. ,  DEWEY, Gilbert ,  CHOI, Chi-hing ,  Kennel, Harold W. ,  KRIST, Brian J. ,  ALIYARUKUNJU, Ashkar ,  BOMBERGER, Cory ,  SHAH, Rushabh ,  MEHANDRU, Rishabh ,  CEA, Stephen M. ,  MUNASINGHE, Chanaka ,  MURHTY, Anand ,  GHANI, Tahir

IPC分类号： H01L29/06 ,  H01L21/285 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/423 ,  H01L21/336 ,  H01L29/775 ,  H01L27/092 ,  B82Y10/00

摘要： Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.

公开(公告)号：EP4202977A1

公开(公告)日：2023-06-28

申请号：EP22214363.8

申请日：2022-12-16

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  DEWEY, Gilbert ,  GHANI, Tahir ,  HARATIPOUR, Nazila ,  KOBRINSKY, Mauro J. ,  MURTHY, Anand

IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L21/768

摘要： The formation of titanium contacts to silicon germanium (SiGe) comprises the formation of a titanium silicide layer in which the silicon for the titanium silicide layer is provided by flowing silane (disilane, trisilane, etc.) over a titanium layer at an elevated temperature. The titanium silicide layer can help limit the amount of titanium and germanium interdiffusion that can occur across the titanium silicide-silicon germanium interface, which can reduce (or eliminate) the formation of voids in the SiGe layer during subsequent anneal and other high-temperature processes. The surface of the SiGe layer upon which the titanium layer is formed can also be preamorphized via boron and germanium implantation to further improve the robustness of the SiGe layer against microvoid development. The resulting titanium contacts are thermally stable in that their resistance remains substantially unchanged after being subjected to downstream annealing and high-temperature processing processes.

公开(公告)号：EP4300591A1

公开(公告)日：2024-01-03

申请号：EP23173199.3

申请日：2023-05-12

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  ZIGONEANU, Imola ,  DEWEY, Gilbert ,  JAHAGIRDAR, Anant H. ,  KENNEL, Harold W. ,  PATEL, Pratik ,  MURTHY, Anand ,  CHOI, Chi-Hing ,  KOBRINSKY, Mauro J. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

摘要： Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm 2 .

公开(公告)号：EP4203062A1

公开(公告)日：2023-06-28

申请号：EP22208658.9

申请日：2022-11-21

申请人： Intel Corporation

发明人： NANDI, Debaleena ,  BOMBERGER, Cory ,  LANCASTER, Diane ,  DEWEY, Gilbert ,  PATIL, Sandeep K. ,  KOBRINSKY, Mauro J. ,  MURTHY, Anand S. ,  GHANI, Tahir

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

摘要： Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires (406) above a sub-fin. A gate stack (428, 426) is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) titanium silicide conductive contact material (434, 436) on the second pEPI region.

公开(公告)号：EP4156283A1

公开(公告)日：2023-03-29

申请号：EP22191316.3

申请日：2022-08-19

申请人： INTEL Corporation

发明人： GHANI, Tahir ,  MURTHY, Anand ,  DEWEY, Gilbert ,  KOBRINSKY, Mauro ,  BOMBERGER, Cory ,  HARATIPOUR, Nazila ,  NANDI, Debaleena ,  SHAH, Rushabh

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/775 ,  H01L29/45 ,  B82Y10/00 ,  H01L29/36

摘要： PMOS gate-all-around integrated circuit structures having confined p-type epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. P-type epitaxial source or drain structures (358, 359, 360, 364, 366) are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron (358), ii) a second pEPI region of silicon, germanium and boron (359) on the first pEPI region at a contact location, iii) a capping layer comprising silicon (360) over the second pEPI region. A conductive contact material (366) comprising titanium is on the capping layer.The resulting source or drain structure exhibits an ultra-low contact resistance and is thermally stable. Preferably the B-11 boron isotope is used in the source or drain structure.

公开(公告)号：EP4109553A1

公开(公告)日：2022-12-28

申请号：EP22180459.4

申请日：2022-06-22

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  BOMBERGER, Cory ,  DEWEY, Gilbert ,  MURTHY, Anand S. ,  KOBRINSKY, Mauro ,  SHAH, Rushabh ,  CHOI, Chi-Hing ,  KENNEL, Harold W. ,  SAADAT, Omair ,  ONI, Adedapo ,  HARATIPOUR, Nazila ,  GHANI, Tahir

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

摘要： Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.