- 专利标题: PHASE-LOCKED LOOP CIRCUIT AND METHOD FOR CONTROLLING THE SAME
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申请号: EP22187066.0申请日: 2022-07-26
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公开(公告)号: EP4125216A1公开(公告)日: 2023-02-01
- 发明人: YE, Yan , LIANG, Cheng
- 申请人: Silergy Semiconductor Technology (Hangzhou) Ltd
- 申请人地址: CN Zhejiang 310051 No.6, Lianhui Street Xixing Sub-district Binjiang District Hangzhou
- 代理机构: Ström & Gulliksson AB
- 优先权: CN202110852953 20210727
- 主分类号: H03L7/087
- IPC分类号: H03L7/087 ; H03L7/089 ; H03L7/099 ; H03L7/197
摘要:
A phase-locked loop circuit and a method for controlling the phase-locked loop circuit are provided. Multiple values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to multiple desired values of a frequency control word signal and multiple values of a charge pump current control signal respectively corresponding to the multiple desired values of the frequency control word signal are acquired in a calibration mode. In a phase-locked mode, a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the voltage-controlled oscillator capacitor array control signal are determined based on the data acquired in the calibration mode, to control the phase-locked loop circuit to achieve the phase lock. Therefore, an optimal sub-band is directly determined based on the acquired data, thereby shortening the duration spent by the phase-locked loop circuit on achieving phase lock and reducing power consumption of the phase-locked loop circuit in the process of achieving phase lock.
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