公开(公告)号：EP4125216A1

公开(公告)日：2023-02-01

申请号：EP22187066.0

申请日：2022-07-26

申请人： Silergy Semiconductor Technology (Hangzhou) Ltd

发明人： YE, Yan ,  LIANG, Cheng

IPC分类号： H03L7/087 ,  H03L7/089 ,  H03L7/099 ,  H03L7/197

摘要： A phase-locked loop circuit and a method for controlling the phase-locked loop circuit are provided. Multiple values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to multiple desired values of a frequency control word signal and multiple values of a charge pump current control signal respectively corresponding to the multiple desired values of the frequency control word signal are acquired in a calibration mode. In a phase-locked mode, a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the voltage-controlled oscillator capacitor array control signal are determined based on the data acquired in the calibration mode, to control the phase-locked loop circuit to achieve the phase lock. Therefore, an optimal sub-band is directly determined based on the acquired data, thereby shortening the duration spent by the phase-locked loop circuit on achieving phase lock and reducing power consumption of the phase-locked loop circuit in the process of achieving phase lock.