- 专利标题: NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
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申请号: EP22217082.1申请日: 2020-02-03
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公开(公告)号: EP4195258A1公开(公告)日: 2023-06-14
- 发明人: MAHAJAN, Ravindranath V. , MALLIK, Debendra , SHARAN, Sujit , RAORANE, Digvijay
- 申请人: INTEL Corporation
- 申请人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 代理机构: 2SPL Patentanwälte PartG mbB
- 优先权: US201916291314 20190304
- 主分类号: H01L23/38
- IPC分类号: H01L23/38 ; H01L23/538
摘要:
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
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