利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.011 秒)

    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
    1.
    发明公开
    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION 审中-公开

    公开(公告)号：EP4195258A1

    公开(公告)日：2023-06-14

    申请号：EP22217082.1

    申请日：2020-02-03

    申请人： INTEL Corporation

    发明人： MAHAJAN, Ravindranath V. ,  MALLIK, Debendra ,  SHARAN, Sujit ,  RAORANE, Digvijay

    IPC分类号： H01L23/38 ,  H01L23/538

    摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

    BRIDGE HUB TILING ARCHITECTURE
    2.
    发明公开
    BRIDGE HUB TILING ARCHITECTURE 审中-公开

    公开(公告)号：EP3506352A1

    公开(公告)日：2019-07-03

    申请号：EP18209345.0

    申请日：2018-11-29

    申请人： INTEL Corporation

    发明人： COLLINS, Andrew P. ,  RAORANE, Digvijay A. ,  GOMES, Wilfred ,  MAHAJAN, Ravindranath V. ,  SHARAN, Sujit

    IPC分类号： H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01L23/48

    摘要： Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

    INTERCONNECT BRIDGE WITH SIMILAR CHANNEL LENGTHS
    5.
    发明公开
    INTERCONNECT BRIDGE WITH SIMILAR CHANNEL LENGTHS 审中-公开

    公开(公告)号：EP4300575A1

    公开(公告)日：2024-01-03

    申请号：EP23175256.9

    申请日：2023-05-25

    申请人： INTEL Corporation

    发明人： WANG, Lijiang ,  VISWANATHAN, Naren Sreenivas ,  SHARAN, Sujit ,  SUN, Jiwei

    IPC分类号： H01L23/538

    摘要： An electronic device may include an interconnect bridge. The interconnect bridge may include a first electrical routing trace having a first routing length and a corresponding first transit time for a first electrical signal to transmit across the first routing length. The first electrical routing trace may transmit the first electrical signal along a major plane of the interconnect bridge between a first interconnect and a second interconnect. The interconnect bridge may include a routing trace deviation in communication with the first electrical routing trace. The routing trace deviation is outside a direct route between the first interconnect and the second interconnect. The routing trace deviation may alter one or more of capacitance or resistance of the first electrical routing trace and correspondingly alter the first routing time.

    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
    6.
    发明公开
    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION 审中-公开

    公开(公告)号：EP3706165A1

    公开(公告)日：2020-09-09

    申请号：EP20155202.3

    申请日：2020-02-03

    申请人： INTEL Corporation

    发明人： MAHAJAN, Ravindranath ,  MALLIK, Debendra ,  SHARAN, Sujit ,  RAORANE, Digvijay

    IPC分类号： H01L23/38 ,  H01L23/538

    摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
    7.
    发明公开
    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION 审中-实审

    公开(公告)号：EP4340023A2

    公开(公告)日：2024-03-20

    申请号：EP23220590.6

    申请日：2020-02-03

    申请人： INTEL Corporation

    发明人： MAHAJAN, Ravindranath Vithal ,  MALLIK, Debendra ,  SHARAN, Sujit ,  RAORANE, Digvijay

    IPC分类号： H01L23/538

    摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

    SILICON GROOVE ARCHITECTURES AND MANUFACTURING PROCESSES FOR PASSIVE ALIGNMENT IN A PHOTONICS DIE
    9.
    发明公开
    SILICON GROOVE ARCHITECTURES AND MANUFACTURING PROCESSES FOR PASSIVE ALIGNMENT IN A PHOTONICS DIE 审中-公开

    公开(公告)号：EP4020032A1

    公开(公告)日：2022-06-29

    申请号：EP21198753.2

    申请日：2021-09-24

    申请人： Intel Corporation

    发明人： SHARAN, Sujit ,  DESHPANDE, Nitin ,  KARHADE, Omkar ,  LI, Xiaoqian

    IPC分类号： G02B6/36 ,  G02B6/42

    摘要： A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.
    A method for fabricating a groove alignment structure, comprising: applying an etch stop material to a backside of a silicon substrate comprising a photonics die; performing a first etch process to form openings that define locations and widths of a plurality of grooves along a first direction in the silicon substrate; depositing polymer guides in-between the openings, the polymer guides running a same direction as the openings; performing a second etch process on the openings to remove silicon down to the etch stop material to form grooves; depositing an adhesive material into a bottom of the grooves; and inserting an optical fiber of an optical fiber array into respective ones of grooves.