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    WIRELESS CHARGING SYSTEM
    2.
    发明公开
    WIRELESS CHARGING SYSTEM 审中-公开
    无线充电系统

    公开(公告)号：EP3157126A1

    公开(公告)日：2017-04-19

    申请号：EP16202211.5

    申请日：2013-06-28

    申请人： INTEL Corporation

    发明人： DOYLE, Brian S. ,  ALEKSOV, Aleksandar ,  MAHAJAN, Ravindranath V.

    IPC分类号： H02J7/00 ,  H02J50/10 ,  H02J50/80 ,  H02J50/12

    CPC分类号： H02J7/0004 ,  H02J7/0013 ,  H02J7/0042 ,  H02J7/0044 ,  H02J7/025 ,  H02J50/00 ,  H02J50/10 ,  H02J50/12 ,  H02J50/40 ,  H02J50/70 ,  H02J50/80 ,  Y02B40/90 ,  Y02E60/12

    摘要： A wireless charging system includes a microelectronic package (110) containing a system on chip (120) (an SoC), an energy transfer unit (140), and a software protocol (127). The SoC includes a processing device (121), a memory device (122) coupled to the processing device, and a communications device (123) coupled to the processing device and the memory device. The communications device is capable of communicating wirelessly with an external electronic device (130). The energy transfer unit is capable of transferring energy to the external electronic device. The software protocol is implemented in the memory device and is capable of detecting a charging profile of the external electronic device and capable of adjusting a parameter of the energy transfer unit according to a requirement of the charging profile.

    摘要翻译： 无线充电系统包括包含片上系统（SoC），能量传输单元（140）和软件协议（127）的微电子封装（110）。 SoC包括处理装置（121），耦合到处理装置的存储器装置（122）以及耦合到处理装置和存储器装置的通信装置（123）。 通信设备能够与外部电子设备（130）无线通信。 能量传输单元能够将能量传递到外部电子设备。 所述软件协议在所述存储设备中实现，能够检测所述外部电子设备的充电情况，并且能够根据所述充电情况的要求调整所述能量转移单元的参数。

    DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE
    3.
    发明公开
    DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE 审中-公开

    公开(公告)号：EP3511980A1

    公开(公告)日：2019-07-17

    申请号：EP18211801.8

    申请日：2018-12-11

    申请人： INTEL Corporation

    发明人： GOMES, Wilfred ,  BOHR, Mark T. ,  KUMAR, Rajesh ,  SANKMAN, Robert L. ,  MAHAJAN, Ravindranath V. ,  MC CULLOUGH, Wesley D.

    IPC分类号： H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L25/00 ,  H01L23/538 ,  H01L23/52

    摘要： The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

    WIRELESS CHARGING SYSTEM
    4.
    发明公开
    WIRELESS CHARGING SYSTEM 审中-公开
    无线充电系统

    公开(公告)号：EP2932579A1

    公开(公告)日：2015-10-21

    申请号：EP13866087.3

    申请日：2013-06-28

    申请人： Intel Corporation

    发明人： DOYLE, Brian S. ,  ALEKSOV, Aleksandar ,  MAHAJAN, Ravindranath V.

    IPC分类号： H02J17/00 ,  H02J7/00

    摘要： A wireless charging system includes a microelectronic package (110) containing a system on chip (120) (an SoC), an energy transfer unit (140), and a software protocol (127). The SoC includes a processing device (121), a memory device (122) coupled to the processing device, and a communications device (123) coupled to the processing device and the memory device. The communications device is capable of communicating wirelessly with an external electronic device (130). The energy transfer unit is capable of transferring energy to the external electronic device. The software protocol is implemented in the memory device and is capable of detecting a charging profile of the external electronic device and capable of adjusting a parameter of the energy transfer unit according to a requirement of the charging profile.

    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
    8.
    发明公开
    NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION 审中-公开

    公开(公告)号：EP4195258A1

    公开(公告)日：2023-06-14

    申请号：EP22217082.1

    申请日：2020-02-03

    申请人： INTEL Corporation

    发明人： MAHAJAN, Ravindranath V. ,  MALLIK, Debendra ,  SHARAN, Sujit ,  RAORANE, Digvijay

    IPC分类号： H01L23/38 ,  H01L23/538

    摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

    BRIDGE HUB TILING ARCHITECTURE
    9.
    发明公开
    BRIDGE HUB TILING ARCHITECTURE 审中-公开

    公开(公告)号：EP3506352A1

    公开(公告)日：2019-07-03

    申请号：EP18209345.0

    申请日：2018-11-29

    申请人： INTEL Corporation

    发明人： COLLINS, Andrew P. ,  RAORANE, Digvijay A. ,  GOMES, Wilfred ,  MAHAJAN, Ravindranath V. ,  SHARAN, Sujit

    IPC分类号： H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01L23/48

    摘要： Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.