A display panel (1) and a display device (100), capable of preventing a serial display phenomenon. The display panel (1) comprises a gate driving circuit (10), multiple clock signal lines (CLK1-CLKm), a timing controller (300), and multiple anti-serial circuits (400); the timing controller (300) is configured to provide a first clock signal; the multiple anti-serial circuits (400) are connected to the timing controller (300) and the multiple clock signal lines (CLK1-CLKm), and are configured to adjust the first clock signal provided by the timing controller (300) into a second clock signal and output the second clock signal to the multiple clock signal lines (CLK1-CLKm); a falling time (t1) of the falling edge of the second clock signal is less than a falling time (t2) of the falling edge of the first clock signal; the gate driving circuit (10) comprises multiple cascaded shift register units (500) that are respectively connected to the multiple clock signal lines (CLK1-CLKm); the gate driving circuit (10) is configured to output the second clock signal as an output signal line by line; and each of the multiple anti-serial circuits (400) comprises at least one resistor (R1-Rm) and at least one inductor (L1-Lm).