-
公开(公告)号：EP4207175A1
公开(公告)日：2023-07-05
申请号：EP21935593.0
申请日：2021-04-09
发明人： CHEN, Dongchuan , LIAO, Yanping , MIAO, Yingmeng , ZHANG, Yinlong , YAO, Shulin , SHAO, Xibin , LEE, Seungmin , LIU, Jiantao
摘要： A display driving method, a display driving device, and a display device. The display driving method comprises: when displaying an odd number of frames, providing first parity row data of the odd number of frames to a display array, so that a third parity row of the display array is displayed on the basis of real data of the first parity row data, and so that a fourth parity row of the display array is displayed on the basis of interpolation data of the first parity row data; when displaying an even number of frames, providing second parity row data of an even number of frames to a display panel, so that the fourth parity row of the display array is displayed on the basis of real data of the second parity row data, and so that the third parity row of the display array is displayed on the basis of interpolation data of the second parity row data. Any row of the display array has two rows of charging time before display; if both rows of charging time of any row are used for charging according to corresponding real data thereof, then the row is displayed on the basis of the real data, otherwise the row is displayed on the basis of the interpolation data.
-
公开(公告)号：EP4207149A1
公开(公告)日：2023-07-05
申请号：EP21935801.7
申请日：2021-10-28
发明人： LIAO, Yanping , MIAO, Yingmeng , LEE, Seungmin , SHAO, Xibin , YAO, Shulin , ZHANG, Yinlong , SU, Qiujie , WANG, Cong , CHEN, Dongchuan , LIU, Jiantao
摘要： A display panel and a drive method therefor, and a display apparatus. The display panel (1) comprises a gate drive circuit (10), wherein the gate drive circuit (10) comprises multiple stages of shift registers which are sequentially arranged, the multiple stages of shift registers which are sequentially arranged are combined into N groups of gate drive sub-circuits, and the shift registers in the N groups of gate drive sub-circuits are respectively cascaded. The mth group of gate drive sub-circuits from among the N groups of gate drive sub-circuits comprises an mth-stage shift register and an (m + L*N)th-stage shift register which are cascaded, wherein m is an integer that is greater than or equal to 1 and is less than or equal to N, L is an integer greater than or equal to 1, and N is an even number greater than or equal to 2. By means of the display panel, an H-1Line picture can be clearly displayed without a serial problem, and a test standard of an industrial CM value is met, thereby improving the performance of a display product.
-
公开(公告)号：EP4443508A1
公开(公告)日：2024-10-09
申请号：EP22950965.8
申请日：2022-12-23
发明人： LIAO, Yanping , MIAO, Yingmeng , LIU, Dong , SHAO, Xibin , JIANG, Peng , CHEN, Dongchuan , ZHAO, Panhui , LIU, Jiantao , YANG, Tao , QU, Yingying
IPC分类号： H01L27/12 , G02F1/1362
CPC分类号： G02F1/1362 , H01L27/12
摘要： The present disclosure provides a display substrate, a display panel and a display device. The display substrate includes: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of a layer where the plurality of data lines are positioned away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the layer where the plurality of data lines are positioned, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of a layer where the plurality of gate lines are positioned away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the layer where the plurality of gate lines are positioned, where an orthographic projection of the first electrode on the base substrate is at least within an region surrounded by orthographic projections of respective data lines on the base substrate and orthographic projections of respective gate lines on the base substrate.
-
公开(公告)号：EP3607398A1
公开(公告)日：2020-02-12
申请号：EP17903368.3
申请日：2017-04-01
发明人： WANG, Fangyu , SHAO, Xibin , ZHANG, Zhenyu , CHEN, Dongchuan , QIAN, Xueqiang
IPC分类号： G02F1/1343
-
公开(公告)号：EP4339935A1
公开(公告)日：2024-03-20
申请号：EP21969661.4
申请日：2021-12-31
发明人： SU, Qiujie , BO, Lingdan , CHEN, Dongchuan , LIU, Jiantao , XIAN, Jianbo
IPC分类号： G09G3/36 , H01L27/146 , H05K1/02
摘要： Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a base substrate including a non-display area; a gate drive circuit located in the non-display area, where the gate drive circuit includes a plurality of shift registers, and the plurality of shift registers are divided into a plurality of register sets; and a plurality of signal lead-in lines located in the non-display area, where the plurality of signal lead-in lines are divided into a plurality of line sets, a frame start signal end of one register set is correspondingly and electrically connected to one line set, and two signal lead-in lines of one line set are provided with the signal lead-in line of another line set therebetween.
-
公开(公告)号：EP4207151A1
公开(公告)日：2023-07-05
申请号：EP21942699.6
申请日：2021-10-28
发明人： SHAO, Xibin , LIAO, Yanping , CHEN, Dongchuan , MIAO, Yingmeng , YAO, Shulin , ZHANG, Yinlong , SU, Qiujie , LIU, Jiantao
IPC分类号： G09G3/20
摘要： A display panel (1) and a display device (100), capable of preventing a serial display phenomenon. The display panel (1) comprises a gate driving circuit (10), multiple clock signal lines (CLK1-CLKm), a timing controller (300), and multiple anti-serial circuits (400); the timing controller (300) is configured to provide a first clock signal; the multiple anti-serial circuits (400) are connected to the timing controller (300) and the multiple clock signal lines (CLK1-CLKm), and are configured to adjust the first clock signal provided by the timing controller (300) into a second clock signal and output the second clock signal to the multiple clock signal lines (CLK1-CLKm); a falling time (t1) of the falling edge of the second clock signal is less than a falling time (t2) of the falling edge of the first clock signal; the gate driving circuit (10) comprises multiple cascaded shift register units (500) that are respectively connected to the multiple clock signal lines (CLK1-CLKm); the gate driving circuit (10) is configured to output the second clock signal as an output signal line by line; and each of the multiple anti-serial circuits (400) comprises at least one resistor (R1-Rm) and at least one inductor (L1-Lm).
-
公开(公告)号：EP3420406A1
公开(公告)日：2019-01-02
申请号：EP16840362.4
申请日：2016-08-12
发明人： SHAO, Xibin , CHEN, Dongchuan , LIAO, Yanping
IPC分类号： G02F1/13357
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.017 秒)
