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公开(公告)号：EP4207151A1
公开(公告)日：2023-07-05
申请号：EP21942699.6
申请日：2021-10-28
发明人： SHAO, Xibin , LIAO, Yanping , CHEN, Dongchuan , MIAO, Yingmeng , YAO, Shulin , ZHANG, Yinlong , SU, Qiujie , LIU, Jiantao
IPC分类号： G09G3/20
摘要： A display panel (1) and a display device (100), capable of preventing a serial display phenomenon. The display panel (1) comprises a gate driving circuit (10), multiple clock signal lines (CLK1-CLKm), a timing controller (300), and multiple anti-serial circuits (400); the timing controller (300) is configured to provide a first clock signal; the multiple anti-serial circuits (400) are connected to the timing controller (300) and the multiple clock signal lines (CLK1-CLKm), and are configured to adjust the first clock signal provided by the timing controller (300) into a second clock signal and output the second clock signal to the multiple clock signal lines (CLK1-CLKm); a falling time (t1) of the falling edge of the second clock signal is less than a falling time (t2) of the falling edge of the first clock signal; the gate driving circuit (10) comprises multiple cascaded shift register units (500) that are respectively connected to the multiple clock signal lines (CLK1-CLKm); the gate driving circuit (10) is configured to output the second clock signal as an output signal line by line; and each of the multiple anti-serial circuits (400) comprises at least one resistor (R1-Rm) and at least one inductor (L1-Lm).
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公开(公告)号：EP4207175A1
公开(公告)日：2023-07-05
申请号：EP21935593.0
申请日：2021-04-09
发明人： CHEN, Dongchuan , LIAO, Yanping , MIAO, Yingmeng , ZHANG, Yinlong , YAO, Shulin , SHAO, Xibin , LEE, Seungmin , LIU, Jiantao
摘要： A display driving method, a display driving device, and a display device. The display driving method comprises: when displaying an odd number of frames, providing first parity row data of the odd number of frames to a display array, so that a third parity row of the display array is displayed on the basis of real data of the first parity row data, and so that a fourth parity row of the display array is displayed on the basis of interpolation data of the first parity row data; when displaying an even number of frames, providing second parity row data of an even number of frames to a display panel, so that the fourth parity row of the display array is displayed on the basis of real data of the second parity row data, and so that the third parity row of the display array is displayed on the basis of interpolation data of the second parity row data. Any row of the display array has two rows of charging time before display; if both rows of charging time of any row are used for charging according to corresponding real data thereof, then the row is displayed on the basis of the real data, otherwise the row is displayed on the basis of the interpolation data.
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公开(公告)号：EP4207149A1
公开(公告)日：2023-07-05
申请号：EP21935801.7
申请日：2021-10-28
发明人： LIAO, Yanping , MIAO, Yingmeng , LEE, Seungmin , SHAO, Xibin , YAO, Shulin , ZHANG, Yinlong , SU, Qiujie , WANG, Cong , CHEN, Dongchuan , LIU, Jiantao
摘要： A display panel and a drive method therefor, and a display apparatus. The display panel (1) comprises a gate drive circuit (10), wherein the gate drive circuit (10) comprises multiple stages of shift registers which are sequentially arranged, the multiple stages of shift registers which are sequentially arranged are combined into N groups of gate drive sub-circuits, and the shift registers in the N groups of gate drive sub-circuits are respectively cascaded. The mth group of gate drive sub-circuits from among the N groups of gate drive sub-circuits comprises an mth-stage shift register and an (m + L*N)th-stage shift register which are cascaded, wherein m is an integer that is greater than or equal to 1 and is less than or equal to N, L is an integer greater than or equal to 1, and N is an even number greater than or equal to 2. By means of the display panel, an H-1Line picture can be clearly displayed without a serial problem, and a test standard of an industrial CM value is met, thereby improving the performance of a display product.
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公开(公告)号：EP4163768A1
公开(公告)日：2023-04-12
申请号：EP20963039.1
申请日：2020-11-30
发明人： SU, Qiujie , LIAO, Yanping , MIAO, Yingmeng , ZHAO, Chongyang , HU, Bo , YIN, Xiaofeng
IPC分类号： G06F3/041 , G06F3/044 , G02F1/1362
摘要： An array substrate and a touch display device are provided. In the array substrate, a first control unit and a second control unit are arranged opposite to each other in a first direction. A plurality of touch sensor blocks includes a first group of electrode blocks and a second group of electrode blocks arranged in the first direction, and a plurality of touch signal lines includes a first group of touch signal lines and a second group of touch signal lines arranged in the first direction. The touch signal lines in the first group of touch signal lines are coupled to the touch sensor blocks in the first group of electrode blocks respectively, and one end of each of the touch signal lines in the first group of touch signal lines is coupled to the first control unit; and the touch signal lines in the second group of touch signal lines are coupled to the touch sensor blocks in the second group of electrode blocks respectively, and one end of each of the touch signal lines in the second group of touch signal lines is coupled to the second control unit.
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公开(公告)号：EP4443508A1
公开(公告)日：2024-10-09
申请号：EP22950965.8
申请日：2022-12-23
发明人： LIAO, Yanping , MIAO, Yingmeng , LIU, Dong , SHAO, Xibin , JIANG, Peng , CHEN, Dongchuan , ZHAO, Panhui , LIU, Jiantao , YANG, Tao , QU, Yingying
IPC分类号： H01L27/12 , G02F1/1362
CPC分类号： G02F1/1362 , H01L27/12
摘要： The present disclosure provides a display substrate, a display panel and a display device. The display substrate includes: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of a layer where the plurality of data lines are positioned away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the layer where the plurality of data lines are positioned, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of a layer where the plurality of gate lines are positioned away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the layer where the plurality of gate lines are positioned, where an orthographic projection of the first electrode on the base substrate is at least within an region surrounded by orthographic projections of respective data lines on the base substrate and orthographic projections of respective gate lines on the base substrate.
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公开(公告)号：EP4155823A1
公开(公告)日：2023-03-29
申请号：EP20966219.6
申请日：2020-12-21
发明人： ZHAO, Chongyang , MIAO, Yingmeng , SUN, Zhihua , QU, Feng , XU, Xiaochun
IPC分类号： G03F9/00
摘要： The embodiments of the present disclosure provide an array substrate, a display panel, and an electronic device. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one sub-pixel unit including at least one first sub-pixel unit is provided on the base substrate, and the at least one first sub-pixel unit includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.
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公开(公告)号：EP4095595A1
公开(公告)日：2022-11-30
申请号：EP21776160.0
申请日：2021-02-02
发明人： HUANG, Jianhua , ZHAO, Chongyang , SUN, Zhihua , MIAO, Yingmeng , QU, Yingying
IPC分类号： G02F1/1345 , G02F1/1362 , H01L23/522
摘要： An array substrate and a display device. The array substrate is provided with a display region (A) and a peripheral wiring region (B) arranged on at least one side of the display region (A). The display region (A) comprises a thin film transistor (12) and a common electrode (13) which are formed on a base substrate (11); and the peripheral wiring region (B) comprises a first lead (18), a gate signal line (19) and a common signal line (20) which are formed on the base substrate (11). The first lead (18) is arranged on the same layer as a gate (120) of the thin film transistor (12) and is electrically connected with the gate (120); the gate signal line (19) is located at the side of the first lead (18) away from the base substrate (11).
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