A hardware accelerator (110) includes processing elements (172) of a neural network, each processing element having a memory (104); a stream switch (155); stream engines (150) coupled to functional circuits (102, 160, 165, 180) via the stream switch (155), wherein the stream engines (150), in operation, generate data streaming requests to stream data to and from functional circuits of the plurality of functional circuits (102, 160, 165, 180); a first system bus interface (158) coupled to the stream engines (150); a second system bus interface (184) coupled to the processing elements (172); and mode control circuitry (176), which, in operation, sets respective modes of operation for the plurality of processing elements (172). The modes of operation include: a compute mode of operation in which the processing element (172) performs computing operations using the memory (104) associated with the processing element; and a memory mode of operation in which the memory (104) associated with the processing element (172) performs memory operations, bypassing the stream switch (155), via the second system bus interface (184).