- 专利标题: PROCESS FOR GENERATING PHYSICAL IMPLEMENTATION GUIDANCE DURING THE SYNTHESIS OF A NETWORK-ON-CHIP
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申请号: EP24172264.4申请日: 2024-04-24
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公开(公告)号: EP4455929A2公开(公告)日: 2024-10-30
- 发明人: CHARIF, Amir , VAN RUYMBEKE, Xavier , BALES, Mark
- 申请人: Arteris, Inc.
- 申请人地址: US Campbell, CA 95008 595 Millich Dr., Suite 200
- 代理机构: Sach, Greg Robert
- 优先权: US202318305382 20230424
- 主分类号: G06F30/392
- IPC分类号: G06F30/392 ; G06F30/394 ; G06F30/398 ; G06F115/02 ; G06F115/08 ; G06F119/12 ; G06F119/06
摘要:
System and methods are disclosed for augmenting a synthesized NoC, with data that guides a physical implementation of the NoC topology in a way that coincides with the topology synthesis result and reduces timing violations in the final physical design. The system generates physical implementation guidance, which is during physical implementation of the synthesized NoC. The system inserts a link as a pipeline placeholder and a minimum set of created module regions are assigned to a specific link of the topology. Each route has a new link and corresponding module region inserted into the physical path.
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