公开(公告)号：EP4455929A2

公开(公告)日：2024-10-30

申请号：EP24172264.4

申请日：2024-04-24

申请人： Arteris, Inc.

发明人： CHARIF, Amir ,  VAN RUYMBEKE, Xavier ,  BALES, Mark

IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F115/02 ,  G06F115/08 ,  G06F119/12 ,  G06F119/06

摘要： System and methods are disclosed for augmenting a synthesized NoC, with data that guides a physical implementation of the NoC topology in a way that coincides with the topology synthesis result and reduces timing violations in the final physical design. The system generates physical implementation guidance, which is during physical implementation of the synthesized NoC. The system inserts a link as a pipeline placeholder and a minimum set of created module regions are assigned to a specific link of the topology. Each route has a new link and corresponding module region inserted into the physical path.

公开(公告)号：EP4404097A1

公开(公告)日：2024-07-24

申请号：EP24152431.3

申请日：2024-01-17

申请人： Arteris, Inc.

发明人： CHARIF, Amir ,  VAN RUYMBEKE, Xavier

IPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/394 ,  G06F119/20 ,  G06F115/02

CPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/394 ,  G06F2115/0220200101 ,  G06F2119/2020200101

摘要： System and methods are disclosed for generation and synthesis of networks, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.