公开(公告)号：EP3738145B1

公开(公告)日：2025-02-12

申请号：EP18830104.8

申请日：2018-12-10

Inventor： CORREALE, Anthony Jr. ,  ILES, Philip Michael

IPC: G06F30/337 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  G06F30/394 ,  G06F30/392 ,  G06F113/04 ,  G06F119/06 ,  G06F119/08

公开(公告)号：EP3096199B1

公开(公告)日：2024-11-20

申请号：EP16169245.4

申请日：2016-05-11

Inventor： Miller, Gary ,  Gay, James ,  Lubbers, Gilford ,  Zhong, Geng

IPC: G06F1/10 ,  G06F1/12 ,  G06F13/16 ,  H03K5/135 ,  H03K19/17736 ,  G06F13/40 ,  G06F30/3312 ,  G06F30/394 ,  G06F30/396 ,  G06F119/12

公开(公告)号：EP4411585A1

公开(公告)日：2024-08-07

申请号：EP24153271.2

申请日：2024-01-22

Applicant: Apple Inc.

Inventor： CHANDAKA, Venu ,  Mulage, Preeti S.

IPC: G06F30/394

CPC classification number: G06F30/394

Abstract: As the complexity of integrated circuits (ICs) increase (e.g., more sophisticated circuit designs and/or more circuit components integrated into the ICs), digital routing channels connecting various circuit components may occupy more chip area to prevent certain interferences (e.g., interference caused by a channel crosstalk or coupling between adjacent digital routing channels), resulting in certain problems, such as reduced efficiency of chip area usage and increased power consumption. To solve such problems, inverter staggering circuits and/or coaxial shielding of digital routing channels may be used in the ICs to mitigate the interferences. The inverter staggering circuits and/or coaxial shielding may improve the robustness of digital signals transmitted via the digital routing channels with reduced interferences, resulting in enhanced signal integrity, chip area utilization, power saving, and the like.

公开(公告)号：EP4109522B1

公开(公告)日：2024-06-26

申请号：EP22165560.8

申请日：2022-03-30

IPC: H01L23/522 ,  H01L23/528 ,  G06F30/394 ,  G06F30/398

CPC classification number: H01L23/522 ,  H01L23/528 ,  G06F30/398 ,  G06F30/394

公开(公告)号：EP4381414A1

公开(公告)日：2024-06-12

申请号：EP22764921.7

申请日：2022-07-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： VENKATRAMANI, Rajagopalan ,  GADDI, Renato Dimatula ,  MARTINEZ, Liane ,  SANTOS, Warren Alexander ,  SURELL, Dennis Glenn Lozanta

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F115/12 ,  G06F113/18

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F2115/1220200101 ,  G06F2113/1820200101

公开(公告)号：EP2529327B1

公开(公告)日：2024-02-28

申请号：EP11737440.5

申请日：2011-01-14

Inventor： QIAO, Changge ,  CHU, Chi-Min ,  LIN, Jing, C.

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F119/12

公开(公告)号：EP4218053A1

公开(公告)日：2023-08-02

申请号：EP21758979.5

申请日：2021-08-04

Applicant: QUALCOMM INCORPORATED

Inventor： VANG, Foua ,  LIM, Hyeokjin ,  KANG, Seung Hyuk ,  BOYNAPALLI, Venugopal ,  ARORA, Shitiz

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  G06F30/394

公开(公告)号：EP4158474A1

公开(公告)日：2023-04-05

申请号：EP21715698.3

申请日：2021-03-02

Applicant: Microsoft Technology Licensing, LLC

Inventor： VASQUEZ LOPEZ, Daniel ,  RENERIS, Kenneth ,  LEE, Jason Michael ,  GOULDING, Michael B. ,  ACCISANO, Paul W. ,  LIPKA, Matus ,  KUESEL, Jamie Randall ,  GATTA, Srinivas Raghu

IPC: G06F9/50 ,  G06F30/392 ,  G06F30/394 ,  H01L39/00 ,  G06F9/48

公开(公告)号：EP4068144A2

公开(公告)日：2022-10-05

申请号：EP22165160.7

申请日：2022-03-29

Applicant: Phytium Technology Co., Ltd.

Inventor： LUAN, Xiaokun ,  HUANG, Wei ,  BIAN, Shaoxian ,  DENG, Yu ,  JIANG, Jianfeng ,  SUN, Yongfeng ,  CHEN, Zhanzhi ,  JIN, Wenjiang ,  WANG, Cuina ,  TANG, Tao

IPC: G06F30/394 ,  G06F30/398 ,  G06F119/12

Abstract: An integrated circuit physical design wiring and optimisation method includes, in a first physical design wiring process, performing physical design wiring with a weight of each of one or more signal lines set to a first weight and a weight of a clock line set to a second weight (101), extracting a violation signal line with a time sequence violation during the first physical design wiring process (102), and in a second physical design wiring process, re-performing physical design wiring on the violation signal line, a remaining signal line other than the violation signal line, and the clock line with the weight of the violation signal line set to a third weight greater than the first weight. The first weight is less than or equal to the second weight (103).

公开(公告)号：EP3462484B1

公开(公告)日：2021-04-14

申请号：EP18190102.6

申请日：2018-08-21

Inventor： ALEKSOV, Aleksandar ,  SARKAR, Arnab ,  SAIN, Arghya ,  DARMAWIKARTA, Kristof ,  BRAUNISCH, Henning ,  PARMAR, Prashant D. ,  SHARAN, Sujit ,  SWAN, Johanna M. ,  EID, Feras

IPC: H01L23/522 ,  H05K1/02 ,  H01L23/66 ,  H01L23/528 ,  G06F30/39 ,  G06F30/394 ,  G06F113/18 ,  H01L23/00