A semiconductor device includes gate structures (300) on an insulation structure (140, 420), the gate structures disposed in a second direction (D2) substantially parallel to an upper surface of the insulation structure, source/drain layers at opposite sides, respectively, of each gate structure in a first direction (D1) intersecting the second direction, semiconductor patterns (134) disposed in a third direction (D3) substantially perpendicular to the upper surface of the insulation structure, the semiconductor patterns extending through each of the gate structures and contacting the source/drain layers, a first division pattern (150) between the gate structures, and a connection pattern (370) extending into and contacting an upper portion of the first division pattern and upper portions of the gate structures adjacent to the first division pattern, a lower surface of the connection pattern being lower than upper surfaces of the gate structures and an upper surface of the connection pattern being higher than the upper surfaces of the gate structures.