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    INTEGRATED CIRCUIT DEVICE
    1.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：EP4407669A1

    公开(公告)日：2024-07-31

    申请号：EP24154349.5

    申请日：2024-01-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HWANG, Donghoon ,  HWANG, Inchan ,  KIM, Hyojin

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/423

    CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/535 ,  H01L29/42392

    Abstract: An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.

    SEMICONDUCTOR DEVICES
    2.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：EP4495987A2

    公开(公告)日：2025-01-22

    申请号：EP24186783.7

    申请日：2024-07-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KIM, Hyojin ,  HWANG, Donghoon ,  KANG, Myungil

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes gate structures (300) on an insulation structure (140, 420), the gate structures disposed in a second direction (D2) substantially parallel to an upper surface of the insulation structure, source/drain layers at opposite sides, respectively, of each gate structure in a first direction (D1) intersecting the second direction, semiconductor patterns (134) disposed in a third direction (D3) substantially perpendicular to the upper surface of the insulation structure, the semiconductor patterns extending through each of the gate structures and contacting the source/drain layers, a first division pattern (150) between the gate structures, and a connection pattern (370) extending into and contacting an upper portion of the first division pattern and upper portions of the gate structures adjacent to the first division pattern, a lower surface of the connection pattern being lower than upper surfaces of the gate structures and an upper surface of the connection pattern being higher than the upper surfaces of the gate structures.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-实审

    公开(公告)号：EP4345874A2

    公开(公告)日：2024-04-03

    申请号：EP23187220.1

    申请日：2023-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HWANG, Donghoon ,  KANG, Myungil ,  GWAK, Minchan ,  KIM, Kyungho ,  CHO, Kyung Hee ,  CHOI, Doyoung

    IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: A three-dimensional semiconductor device includes a first active region on a substrate (100), the first active region including a lower channel pattern and a lower source/drain pattern (LSD1) connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern (USD1) connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact (LCT) electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact (AC1) coupled to the lower contact, and a second active contact (AC2) coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.

    SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP4513543A1

    公开(公告)日：2025-02-26

    申请号：EP24168133.7

    申请日：2024-04-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： PARK, Wooseok ,  SONG, Wookhwan ,  HWANG, Donghoon ,  KANG, Myungil ,  RYU, Taehyun ,  LEE, Namhyun

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/775 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  B82Y10/00

    Abstract: A semiconductor device may include a first active pattern, a second active pattern spaced apart at a first distance from the first active pattern, a third active pattern spaced apart at a second distance from the second active pattern, a first device isolation layer between the first and second active patterns, a second device isolation layer between the second and third active patterns, a first channel structure overlapping the first active pattern, a second channel structure overlapping the second active pattern, a third channel structure overlapping the third active pattern, and a separation dielectric layer between the first and second channel structures. The separation dielectric layer may overlap the first device isolation layer. A level of a top surface of the first device isolation layer may be higher than a level of a top surface of the second device isolation layer.

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