PROBLEM TO BE SOLVED: To provide a multilayer wiring board for preventing a load from being applied to design by efficiently drawing out a wiring pattern from a pad arrangement region.
SOLUTION: In the multilayer wiring board 30, the pad arrangement region, where a connection pad 12 to which a semiconductor element is flip-chip connected is disposed in a square grid shape, is provided on a substrate, and the multilayer wiring board 30 has a wiring pattern, where the other end is drawn out of the connection pad 12 to the outside of the pad arrangement region. A pad non-arrangement region is periodically provided along the outer periphery of the pad arrangement region. When the pitch of the connection pad 12, a connection pad diameter, the minimum spacing between the wiring patterns and that between the wiring pattern and the connection pad 12, the minimum wiring width of the wiring pattern, and the number of columns and the number of rows where the pad 12 is not disposed in the pad non-arrangement region are set to P, d, s, w, Ndl, and Ndr, respectively, the connection pad 12 and the wiring patterns are disposed in the arrangement meeting a formula of ((Ndl+1)P-d-s)/(w+s)≥2Ndr+Ndl.
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