Invention Patent
- Patent Title: How to handle processing the wafer, system and computer program for the
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Application No.: JP2003514592Application Date: 2002-07-12
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Publication No.: JP4377224B2Publication Date: 2009-12-02
- Inventor: ピー.シャンムガサンドラム アルルクマー , ティー.スクワーム アレキサンダー , ピー.レイス テリー
- Applicant: アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated
- Assignee: アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated
- Current Assignee: アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated
- Priority: US30514001 2001-07-16; US13540502 2002-05-01
- Main IPC: H01L21/02
- IPC: H01L21/02 ; G05B19/418 ; G05B23/02 ; G06F19/00 ; H01L21/00 ; H01L21/66
Abstract:
Semiconductor wafers are processed in conjunction with a manufacturing execution system using a run-to-run controller and a fault detection system. A recipe is received from the manufacturing execution system by the run-to-run controller for controlling a tool. The recipe includes a setpoint for obtaining one or more target wafer properties. Processing of the wafers is monitored by measuring processing attributes including fault conditions and wafer properties using the fault detection system and one or more sensors. Setpoints of the recipe may be modified at the run-to-run controller according to the processing attributes to maintain the target wafer properties, except in cases when a fault condition is detected by the fault detection system. Thus, data acquired in the presence of tool or wafer fault conditions are not used for feedback purposes. In addition, fault detection models may be used to define a range of conditions indicative of a fault condition. In these cases, the fault detection models may be modified to incorporate, as parameters, setpoints of a recipe modified by a run-to-run controller.
Public/Granted literature
- JP2005522018A Integration of fault detection and run between the control Public/Granted day:2005-07-21
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