PROBLEM TO BE SOLVED: To shorten a compiling processing time accompanying a change of a probe node and to improve the operation efficiency of circuit debugging by securing a specific number of I/Os for prove nodes by programmable gate arrays(FPGA) and dividing an ASIC circuit according to the number of the I/Os. SOLUTION: An I/O 18a of an FPGA 12 is connected to an external terminal 20 for a probe node, an I/O 18b is used for a connection between FPGAs 12, and an I/O 18c is connected to an external terminal 22 for a target system, thereby enabling the connection with the target system 23. Net list data on ASIC circuit constitution obtained in an initial design stage are read in a control and evaluation device 26 to generate data to be assigned to the FPGAs 12. Then the control and evaluation device 26 generates arrangement and wiring data by the FPHGAs 12 and repeats this until data for connecting the final internal net in the FPGAs 12 to the I/O 18a for the probe is generated.