本发明提供一种晶圆级芯片数组，包含一半导体晶圆，具有至少二芯片相邻排列以及一承载层，各该芯片具有一上表面及一下表面，且包含至少一电子组件于该上表面，该承载层覆盖于各该芯片之上表面；以及至少一外延线保护块，配置于该承载层之下且位于该至少二芯片之间，该外延线保护块之厚度小于该芯片之厚度，其中，该外延线保护块内部具有至少一外延线。此外，本发明亦提供该晶圆级芯片数组所制作的芯片封装体及其制造方法。

A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.