本发明系揭露一种半导体基板包含外延区、本体区和源极区；交叉氮化物压盖-有源沟槽闸极堆栈（ANCTGS）和自引导接触增强型插头（SGCEP）设置在半导体基板上方，并且部分嵌入在源极区、本体区和外延区中，构成沟槽闸极MOSFET数组。每个氮化物压盖-有源沟槽闸极堆栈都包含多晶硅沟槽闸极堆栈，嵌入在闸极氧化物壳中，以及氮化硅垫片盖，覆盖多晶硅沟槽闸极顶部；每个自引导接触增强型插头都包含底部紧密接触增强部分（ICES），准确定位至其附近的氮化物压盖-有源沟槽闸极堆栈；顶部远程接触增强部分（DCES），具有横向相对于邻近氮化物压盖-有源沟槽闸极堆栈的定位偏差；以及中间锥形过渡段（TTS）位于底部紧密接触增强部分和顶部远末端接触增强部分之间，并且桥接底部紧密接触增强部分和顶部远末端接触增强部分；在MOSFET数组上方的带图案的电介质区上方的带图案的金属层，借由自引导接触增强型插头构成子引导的源极和本体接头。

A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFETarray. Each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shelland a silicon nitride spacer cap covering the top of the polysilicon trench gate; each SGCEP comprises a lower intimate contact enhancement section (ICES) in accurate registration to itsneighboring ANCTGS; an upper distal contact enhancement section (DCES) having a lateral misregistration (LTMSRG) to the neighboring ANCTGS; and an intervening tapered transitional section (TTS) bridging the ICES and the DCES; a patterned metal layer atop the patterned dielectric regionatop the MOSFET array forms self-guided source and body contacts through the SGCEP.