揭露用于形成垂直晶体管架构的技术。依照一些实施例，半导体层系设置于一下互连层上方且被图案化成为一守则、半守则、或不守则数组的复数个垂直半导体主体(例如，奈米线及/或其他三维半导体结构)，如对一给定目标应用或最终用途所期望。之后，依照一些实施例，在一上互连层之后形成了围绕该些垂直半导体主体之每个(或一些子集)的主动信道部分的一闸极层。在处理期间，一给定垂直半导体主体可能可选地被移除且依照一些实施例，(1)被空白以提供一虚拟信道；或(2)被替换成一导电插件以提供一通孔或其他层间绕线。能以多个迭代来进行处理，例如，用以提供任何标准及/或定制配置的多级/堆栈垂直晶体管电路架构。

Techniques are disclosed for forming vertical transistor architectures. In accordance with some embodiments, a semiconductor layer is disposed over a lower interconnect layer and patterned into a plurality of vertical semiconductor bodies (e.g., nanowires and/or other three-dimensional semiconductor structures) in a regular, semi-regular, or irregular array, as desired for a given target application or end-use. Thereafter, a gate layer surrounding the active channel portion of each (or some sub-set) of the vertical semiconductor bodies is formed, followed by an upper interconnect layer, in accordance with some embodiments. During processing, a given vertical semiconductor body optionally may be removed and, in accordance with some embodiments, either: (1) blanked to provide a dummy channel; or (2) replaced with an electrically conductive plug to provide a via or other inter-layer routing. Processing can be performed in multiple iterations, for example, to provide multi-level/stacked vertical transistor circuit architectures of any standard and/or custom configuration.