以第一与第二闸极各自定义第一P信道（P channel）晶体管与第一N信道（N channel）晶体管。该第二闸极与该第一闸极系电气相连。以第三与第四闸极各自定义第二P信道晶体管与第二N信道晶体管。该第四闸极与该第三闸极系电气相连。第一P信道晶体管、第一N信道晶体管、第二P信道晶体管、与第二N信道晶体管中每一者具有与共享节点电气相连的各自扩散端。第一、第二、第三、与第四闸极中每一者系定义成沿着若干平行指向的闸极轨道中任一个而延伸，不实质接触与毗邻的闸极轨道相关之任一逻辑门阶层特征部布局信道内所定义的逻辑门阶层特征部。

A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.