- 专利标题： Through silicon via layout pattern
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申请号： US13478815申请日： 2012-05-23
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公开(公告)号： US10002820B2公开(公告)日： 2018-06-19
- 发明人: Sun-Rong Jan , Che-Yu Yeh , Chee Wee Liu , Chien-Hua Huang , Bing J. Sheu
- 申请人： Sun-Rong Jan , Che-Yu Yeh , Chee Wee Liu , Chien-Hua Huang , Bing J. Sheu
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater Matsil, LLP
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L23/52 ; H01L29/40
摘要：
A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.
公开/授权文献
- US20130221534A1 Through Silicon Via Layout Pattern 公开/授权日：2013-08-29
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