Invention Grant
- Patent Title: Inter-processor bus link and switch chip failure recovery
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Application No.: US14598640Application Date: 2015-01-16
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Publication No.: US10007629B2Publication Date: 2018-06-26
- Inventor: Thomas Wicki , David Smentek , Sumti Jairath , Kathirgamar Aingaran , Ali Vahidsafa , Paul Loewenstein
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood Shores
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F13/40 ; G06F11/30 ; G06F11/22

Abstract:
A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.
Public/Granted literature
- US20160210255A1 INTER-PROCESSOR BUS LINK AND SWITCH CHIP FAILURE RECOVERY Public/Granted day:2016-07-21
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