公开(公告)号：US20160019149A1

公开(公告)日：2016-01-21

申请号：US14584755

申请日：2014-12-29

Applicant: Oracle International Corporation

Inventor： Ramaswamy Sivaramakrishnan ,  Serena Leung ,  David Smentek

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/6024 ,  Y02D10/13

Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.

Abstract translation: 公开了一种高速缓冲存储器，其选择性地启用和禁用来自系统存储器的推测性读取。 高速缓存存储器可以包括多个分区和多个寄存器。 每个寄存器可以被配置为存储指示针对相应分区的先前请求的返回数据的源的数据。 电路可以被配置为接收对给定分区的数据请求。 电路还可以被配置为读取与给定分区相对应的寄存器的内容，并且依赖于寄存器的内容来启动推测读取。

公开(公告)号：US10007629B2

公开(公告)日：2018-06-26

申请号：US14598640

申请日：2015-01-16

Applicant: Oracle International Corporation

Inventor： Thomas Wicki ,  David Smentek ,  Sumti Jairath ,  Kathirgamar Aingaran ,  Ali Vahidsafa ,  Paul Loewenstein

IPC: G06F11/00 ,  G06F13/40 ,  G06F11/30 ,  G06F11/22

CPC classification number: G06F13/4022 ,  G06F11/221 ,  H04L12/00 ,  H04L12/4625

Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

公开(公告)号：US09734071B2

公开(公告)日：2017-08-15

申请号：US14713053

申请日：2015-05-15

Applicant: Oracle International Corporation

Inventor： Serena Leung ,  Ramaswamy Sivaramakrishnan ,  Joann Lam ,  David Smentek

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0846 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/0802

CPC classification number: G06F12/0848 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/282 ,  G06F2212/621

Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.

公开(公告)号：US09892039B2

公开(公告)日：2018-02-13

申请号：US14691971

申请日：2015-04-21

Applicant: Oracle International Corporation

Inventor： Mark Luttrell ,  David Smentek ,  Ramaswamy Sivaramakrishnan ,  Serena Leung

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/622

Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.

公开(公告)号：US20160210255A1

公开(公告)日：2016-07-21

申请号：US14598640

申请日：2015-01-16

Applicant: Oracle International Corporation

Inventor： Thomas Wicki ,  David Smentek ,  Sumti Jairath ,  Kathirgamar Aingaran ,  Ali Vahidsafa ,  Paul Loewenstein

IPC: G06F13/40 ,  G06F11/22 ,  G06F11/30

CPC classification number: G06F13/4022 ,  G06F11/221 ,  H04L12/00 ,  H04L12/4625

Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

Abstract translation: 公开了一种系统，其中系统可以包括多个总线开关和多个处理器。 每个处理器可以耦合到每个总线开关。 每个处理器可以被配置为启动数据到给定总线开关的传输，并检测到给定总线开关的相应链路是否不可操作。 响应于检测到不可操作的链接到第一总线交换机，给定处理器可以进一步被配置为经由至少第二总线交换机向至少一个其他处理器发送通知消息，并且从一个第二总线交换机去除对应于不可操作链路的路由信息 首先注册 响应于从给定处理器接收到通知消息，至少一个其他处理器可以被配置为从第二寄存器去除对应于不可操作链路的附加路由信息。

公开(公告)号：US10120800B2

公开(公告)日：2018-11-06

申请号：US14584755

申请日：2014-12-29

Applicant: Oracle International Corporation

Inventor： Ramaswamy Sivaramakrishnan ,  Serena Leung ,  David Smentek

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0862

Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.

公开(公告)号：US20160335184A1

公开(公告)日：2016-11-17

申请号：US14713053

申请日：2015-05-15

Applicant: Oracle International Corporation

Inventor： Serena Leung ,  Ramaswamy Sivaramakrishnan ,  Joann Lam ,  David Smentek

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/282 ,  G06F2212/621

Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.

Abstract translation: 公开了一种用于窥探高速缓存的方法和装置。 在一个实施例中，系统包括多个处理节点和由每个处理节点共享的高速缓存。 高速缓存被分区，使得每个处理节点仅使用一个分配的分区。 如果处理节点对其分配的缓存分区的查询导致错过，则高速缓存控制器可以确定是否窥探其他分区以搜索所请求的信息。 可以基于从该分区中的先前错过所获得的请求信息的历史来进行确定。

公开(公告)号：US20160314069A1

公开(公告)日：2016-10-27

申请号：US14691971

申请日：2015-04-21

Applicant: Oracle International Corporation

Inventor： Mark Luttrell ,  David Smentek ,  Ramaswamy Sivaramakrishnan ,  Serena Leung

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/622

Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.

Abstract translation: 公开了一种使用现有高速缓存资源执行非时间写入组合的方法和装置。 在一个实施例中，一种方法包括执行处理器核心上的第一线程，第一线程包括第一块初始化存储（BIS）指令。 可以响应于BIS指令执行缓存查询，并且如果查询导致高速缓存未命中，则高速缓存行可以以无序的脏状态安装在高速缓存中，其中它是由第一线程专有的。 第一BIS指令和一个或多个附加BIS指令可以将数据从第一处理器核心写入第一高速缓存行。 在接收到高速缓存一致性响应之后，可以将第一高速缓存行的状态改变为不再对第一线程排斥的有序脏状态。