A compact signal averaging circuit having an input, a first switch operatively connected to the input, a second switch operatively connected to the first switch, wherein the first switch is coupled to the circuit between the input and the second switch, a first FET having a gate, a source and a drain, wherein the gate is operatively connected to the circuit between the first switch and the second switch, a second FET comprising a gate, a source and a drain, wherein the source is operatively connected to a voltage supply and to the second switch, and an output operatively connected to the first FET drain and the second FET drain.