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1.发明申请公开(公告)号：US20170031012A1
公开(公告)日：2017-02-02
申请号：US14813159
申请日：2015-07-30
发明人： Allen W Hairston , Gary M Madison
IPC分类号： G01S7/497
CPC分类号： G01S7/497 , G01S17/105 , G01S17/89
摘要： The invention measures the frequency of a heterodyne laser radar (LADAR) system signal in the input cell of a focal plane array (FPA). Embodiments amplify the return signal, and drive it into a counter for a fixed period of time. The frequency is the number of counts divided by the count time. An example design amplifier amplifies the return of a single photon response of an avalanche photodiode with a gain of 100 into a digital signal level at a 200 MHz rate with only 84 μW, demonstrating the feasibility of the approach.
摘要翻译： 本发明测量焦平面阵列（FPA）的输入单元中的外差激光雷达（LADAR）系统信号的频率。 实施例放大返回信号，并将其驱动到计数器一段固定的时间。 频率是计数次数除以计数时间。 一个示例设计放大器将具有100增益的雪崩光电二极管的单个光子响应的返回放大到200MHz速率的数字信号电平，仅具有84μW，表明该方法的可行性。
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公开(公告)号：US10079986B1
公开(公告)日：2018-09-18
申请号：US15694307
申请日：2017-09-01
发明人： Allen W Hairston
CPC分类号： H04N5/359 , H04N5/3559 , H04N5/37455 , H04N5/378
摘要： A high density, high speed ROIC uses in-pixel integration capacitors and comparators to convert each pixel charge to a train of pulse spikes which increment a capacitor to successive, discrete charge values that represent a digital, non-binary count value of an in-pixel multi-value digital counter (MVDC). The MVDC can include a plurality of stages whereby comparators limit the maximum count of each stage and increment subsequent stages. The maximum count can be a power of two for subsequent direct ADC conversion to binary. The count values and the residual integration capacitor charge can be read out by ramping the comparator reference inputs and measuring the comparator output timings, effectively forming partially in-pixel single-slope ADC's. The comparators can include temporary internal positive feedback to maintain consistency of the spike pulses to better than 10%.
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公开(公告)号：US10009014B1
公开(公告)日：2018-06-26
申请号：US15668119
申请日：2017-08-03
发明人： Allen W Hairston
CPC分类号： H03H19/004 , G06F7/544 , G06F7/70
摘要： A compact signal averaging circuit having an input, a first switch operatively connected to the input, a second switch operatively connected to the first switch, wherein the first switch is coupled to the circuit between the input and the second switch, a first FET having a gate, a source and a drain, wherein the gate is operatively connected to the circuit between the first switch and the second switch, a second FET comprising a gate, a source and a drain, wherein the source is operatively connected to a voltage supply and to the second switch, and an output operatively connected to the first FET drain and the second FET drain.
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公开(公告)号：US10992895B2
公开(公告)日：2021-04-27
申请号：US15985237
申请日：2018-05-21
发明人： Allen W Hairston , Daniel P Lacroix
IPC分类号： G01J5/00 , H04N5/378 , H04N5/369 , H01L27/146 , H04N5/33
摘要： Methods and systems for enabling an approximation of true snapshot integration by lowering total power requirements, total detector bias current, integrated charge per detector and detector impedance while allowing for higher ROIC input noise through the use of microbolometer photodetectors, super-pixels, and techniques for their use are herein provided.
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公开(公告)号：US10447293B1
公开(公告)日：2019-10-15
申请号：US16206151
申请日：2018-11-30
发明人： Allen W Hairston
摘要： A system and method is provided for analog to digital conversion, the system having: a front end whereby a current is converted to digital pulses; and a back end with a coarse conversion unit outputting a pulse count; and a fine conversion unit outputting a count time measurement count; wherein said back end unit is configured to combine said pulse count and said count time measurement to produce a high dynamic range output, said output being the product of the one more than the pulse count and the integration time divided by the sum of the integration time and the count time management count.
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公开(公告)号：US10073168B2
公开(公告)日：2018-09-11
申请号：US14813159
申请日：2015-07-30
发明人： Allen W Hairston , Gary M Madison
CPC分类号： G01S7/497 , G01S17/105 , G01S17/89
摘要： The invention measures the frequency of a heterodyne laser radar (LADAR) system signal in the input cell of a focal plane array (FPA). Embodiments amplify the return signal, and drive it into a counter for a fixed period of time. The frequency is the number of counts divided by the count time. An example design amplifier amplifies the return of a single photon response of an avalanche photodiode with a gain of 100 into a digital signal level at a 200 MHz rate with only 84 μW, demonstrating the feasibility of the approach.
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