Invention Grant
- Patent Title: Method of manufacturing semiconductor device
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Application No.: US15672909Application Date: 2017-08-09
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Publication No.: US10026744B2Publication Date: 2018-07-17
- Inventor: Hideaki Yamakoshi , Takashi Hashimoto , Shinichiro Abe , Yuto Omizu
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2016-157536 20160810
- Main IPC: H01L27/112
- IPC: H01L27/112 ; H01L27/11563

Abstract:
An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.
Public/Granted literature
- US20180047742A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2018-02-15
Information query
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