公开(公告)号：US10777569B2

公开(公告)日：2020-09-15

申请号：US16404095

申请日：2019-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto Omizu ,  Takashi Hashimoto ,  Hideaki Yamakoshi

IPC: H01L21/3065 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L21/28

Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.

公开(公告)号：US10026744B2

公开(公告)日：2018-07-17

申请号：US15672909

申请日：2017-08-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

IPC: H01L27/112 ,  H01L27/11563

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US11049869B2

公开(公告)日：2021-06-29

申请号：US16278951

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki Yamakoshi ,  Shinichiro Abe ,  Takashi Hashimoto ,  Yuto Omizu

IPC: H01L27/115 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/792 ,  H01L27/02 ,  H01L27/12 ,  H01L21/84 ,  H01L21/027 ,  H01L29/08 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3065

Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.

公开(公告)号：US20180286850A1

公开(公告)日：2018-10-04

申请号：US15880212

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Keiichi Maekawa ,  Hideaki Yamakoshi ,  Shinichiro Abe ,  Hideki Makiyama ,  Tetsuya Yoshida ,  Yuto Omizu

IPC: H01L27/02 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/12

CPC classification number: H01L27/0207 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

公开(公告)号：US12137556B2

公开(公告)日：2024-11-05

申请号：US17500297

申请日：2021-10-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto Omizu

IPC: H10B41/35 ,  H01L27/12 ,  H10B43/35

Abstract: A first insulating film is formed on a semiconductor substrate in each of a first region in which a memory transistor is to be formed, a second region in which a selection transistor is to be formed, a third region in which a high-withstand-voltage transistor is to be formed, and a fourth region in which a low-withstand-voltage transistor is to be formed. Subsequently, the first insulating film in each of the first and second regions is removed. A second insulating film is formed on the semiconductor substrate in each of the first and second regions. A third insulating film having a trap level is formed on the second insulating film. The third insulating film in the second region and the second insulating film in the second region are removed. A fourth insulating film is formed on the third insulating film and on the semiconductor substrate in the second region.

公开(公告)号：US10325899B2

公开(公告)日：2019-06-18

申请号：US15880212

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Keiichi Maekawa ,  Hideaki Yamakoshi ,  Shinichiro Abe ,  Hideki Makiyama ,  Tetsuya Yoshida ,  Yuto Omizu

IPC: G11C16/04 ,  H01L27/02 ,  G11C16/12 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11573

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

公开(公告)号：US20180366556A1

公开(公告)日：2018-12-20

申请号：US15957785

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro ABE ,  Takashi Hashimoto ,  Hideaki Yamakoshi ,  Yuto Omizu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L21/8239

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

公开(公告)号：US11145744B2

公开(公告)日：2021-10-12

申请号：US15957785

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro Abe ,  Takashi Hashimoto ,  Hideaki Yamakoshi ,  Yuto Omizu

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/12 ,  H01L27/11573

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

公开(公告)号：US10651188B2

公开(公告)日：2020-05-12

申请号：US16520758

申请日：2019-07-24

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

IPC: H01L27/11568 ,  G11C11/40 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

公开(公告)号：US10483273B2

公开(公告)日：2019-11-19

申请号：US16012362

申请日：2018-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki Yamakoshi ,  Takashi Hashimoto ,  Shinichiro Abe ,  Yuto Omizu

IPC: H01L27/108 ,  H01L27/11563 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.